MIT6_004s09_lec25

MIT6_004s09_lec25 - MIT OpenCourseWare http/ocw.mit.edu For...

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Unformatted text preview: MIT OpenCourseWare http://ocw.mit.edu For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms . 6.004 Computation Structures Spring 2009 L25 – Wrapup Lecture 1 6.004 – Spring 2009 5/12/09 Computer Architecture: Exciting Times Ahead! Prediction is very difficult, especially about the future. -- Neils Bohr The best way to predict the future is to invent it. -- Alan Kay modified 5/4/09 10:17 L25 – Wrapup Lecture 2 6.004 – Spring 2009 5/12/09 You’ve mastered a lot… Fets & voltages Logic gates Combinational logic circuits Combinational contract: discrete-valued inputs complete in/out spec. static discipline Acyclic connections Summary specification Design: sum-of-products simplification muxes, ROMs, PLAs Storage & state Dynamic discipline Finite-state machines Metastability Throughput & latency Pipelining Sequential logic L25 – Wrapup Lecture 3 6.004 – Spring 2009 5/12/09 … a WHOLE lot … Sequential logic CPU Architecture Computing Theory Instruction Set Architectures Beta implementation Pipelined Beta Software conventions Memory architectures ? Interconnect Virtual machines Interprocess communication Operating Systems Real time, Interrupts Parallel Processing Computer Systems MEM MEM CPU DISK I/O I/ O L2 $ Graphics I/O “AGP” bus L25 – Wrapup Lecture 4 6.004 – Spring 2009 5/12/09 6.035 (U, ) Computer Language Engineering What’s next? Some follow-on options… Software Hardware 6.374 (G, ) Analysis and Design of Digital Integrated Circuits 6.033 (U, ) Computer System Engineering 6.111 (U, ) Introductory Digital Systems Laboratory LA for 6.004 UROP Special Topics 6.823 (G, ) Computer System Architecture 6.115 (U, ) Microcomputer Project Laboratory 6.375 (U, ) Complex Digital System Design L25 – Wrapup Lecture 5 6.004 – Spring 2009 5/12/09 Things to look forward to… 6.004 is only an appetizer! Algorithms Arithmetic Signal Processing Language implementation Processors Superscalars Deep pipelines Multicores Systems Software Storage Virtual Machines Networking Languages & Models Python/Java/Ruby/… Objects/Streams/Aspects Networking Tools Design Languages FPGA prototyping Timing Analyzers L25 – Wrapup Lecture 6 6.004 – Spring 2009 5/12/09 Verilog example: Beta Register File // 2-read, 1-write 32-location register file module regfile(ra1,rd1,ra2,rd2,clk,werf,wa,wd); input...
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MIT6_004s09_lec25 - MIT OpenCourseWare http/ocw.mit.edu For...

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