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MIT6_012S09_lec13 - Lecture 13 Digital Circuits(III CMOS...

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Lecture 13 Digital Circuits (III) CMOS CIRCUITS Outline • CMOS Inverter: Propagation Delay • CMOS Inverter: Power Dissipation • CMOS: Static Logic Gates Reading Assignment: Howe and Sodini; Chapter 5, Sections 5.4 & 5.5 1 6.012 Spring 2009 Lecture 13
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1. Complementary MOS (CMOS) Inverter V IN = 0 V OUT = V DD – V GSn = 0 ( < V Tn ) NMOS OFF – V SGp = V DD ( > - V Tp ) PMOS ON V IN = V DD V OUT = 0 – V GSn = V DD ( > V Tn ) NMOS ON – V SGp = 0 ( < - V Tp ) PMOS OFF Circuit schematic: Basic Operation: V IN V OUT V DD C L 2 6.012 Spring 2009 Lecture 13 No power consumption while idle in any logic state!
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2. CMOS inverter: Propagation delay Inverter propagation delay: time delay between input and output signals; figure of merit of logic speed. Typical propagation delays: < 100 ps. C omplex logic system has 10-50 propagation delays per clock cycle. Estimation of t p : use square-wave at input Average propagation delay: t p = 1 2 t PHL + t PLH ( ) V DD V DD 0 V IN V OUT t PHL t PLH 0 50% t t t CYCLE t CYCLE 3 6.012 Spring 2009 Lecture 13
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CMOS inverter: Propagation delay high-to-low During early phases of discharge, NMOS is saturated and PMOS is cut-off. Time to discharge half of charge stored in C L :. t pHL 1 2 charge on C L @ t = 0 NMOS discharge current V IN LO HI V OUT HI LO V DD C L V IN =0 V OUT =V DD V DD t=0 ­ t=0 + C L V IN =V DD V OUT =V DD V DD C L t->infty V IN =V DD V OUT=0 V DD C L 4 6.012 Spring 2009 Lecture 13
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CMOS inverter: Propagation delay high-to-low (contd.) Then: t PHL C L V DD W n L n μ n C ox V DD V Tn ( ) 2 Q L t = 0 ( ) = C L V DD I Dn = W n 2 L n μ n C ox V DD V Tn ( ) 2 Charge in C L at t=0 - : Discharge Current (NMOS in saturation): Graphical Interpretation I D 2 t = t PHL t = 0 + t = 0 V IN = 0V V IN = V OH t PHL t 2 (a) (b) V OUT V OH V OH V OUT V OH V OH 0 0 0 0 5 6.012 Spring 2009 Lecture 13
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CMOS inverter: Propagation delay low-to-high
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