MIT6_012F09_lec09

MIT6_012F09_lec09 - 6.012 - Microelectronic Devices and...

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6.012 - Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 - Posted on Stellar. Due next Wednesday. Qualitative description - MOS in thermal equilibrium Definition of structure: metal/silicon dioxide/p-type Si (Example: n-MOS) Electrostatic potential of metal relative to silicon: φ m Zero bias condition: Si surface depleted if φ m > φ p-Si (typical situation) Negative bias on metal: depletion to flat-band to accumulation Positive bias on metal: depletion to threshold to inversion Quantitative modeling - MOS in thermal equilibrium, v BC = 0 Depletion approximation applied to the MOS capacitor: 1. Flat-band voltage, V FB 2. Accumulation layer sheet charge density, q A * 3. Maximum depletion region width, X DT 4. Threshold voltage, V T 5. Inversion layer sheet charge density, q N * Quantitative modeling - v BC 0; impact of v BC < 0 Voltage between n+ region and p-substrate: |2 φ p-Si | |2 φ p-Si | - v BC Clif Fonstad, 10/8/09 Lecture 9 - Slide 1
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n-Channel MOSFET: Connecting with the npn MOSFET A very similar behavior, and very similar uses. MOSET G S D + + v GS v DS i G i D i v BE v CE i C 0.6 V 0.2 V Forward Active Region FAR Cutoff Cutoff Saturation i C ! ! F i B v CE > 0.2 V i B ! I BS e qV BE /kT Input curve Output family BJT B E C + + v BE v CE i B i C v DS i D Saturation (FAR) Cutoff Linear or Triode i D ! K [v GS - V T (v BS )] 2 /2 ! Clif Fonstad, 10/8/09 Lecture 9 - Slide 2
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p-Si B G + v GS n+ D S v DS v BS + i G i B i D MOS structures An n-channel MOSFET In an n-channel MOSFET, we have two n-regions (the source and the drain), as in the npn BJT, with a p-region producing a potential barrier for electrons between them. In this device, however, it is the voltage on the gate, v GS , that modulates the potential barrier height. The heart of this device is the MOS capacitor, which we will study today. To analyze the MOS capacitor we will use the same depletion approximation that we introduced in conjunction with p-n junctions. Clif Fonstad, 10/8/09 Lecture 9 - Slide 3
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The n-MOS capacitor Right: Basic device with v BC = 0 p-Si n+ B G SiO 2 + v GS (= v GB ) C Below: One-dimensional structure for depletion approximation analysis* Clif Fonstad, 10/8/09 Lecture 9 - Slide 4 B G + p-Si SiO 2 x -t ox 0 v GB * Note: We can't forget the n+ region is there; we will need electrons, and they will come from there.
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Electrostatic potential and net charge profiles φ (x) Zero bias: v GB = 0 -t ox x d φ m x φ p ρ (x) qN A x d x d x -t ox q D * = -qN A x d qN A Clif Fonstad, 10/8/09 Lecture 9 - Slide 5
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Electrostatic potential and net charge profiles φ (x) Depletion: V FB < v GB < 0 -t ox x d φ m x φ p v GB < 0 ρ (x) qN A x d x d x -t ox -qN A x d qN A Clif Fonstad, 10/8/09 Lecture 9 - Slide 6
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This note was uploaded on 11/07/2011 for the course COMPUTERSC 6.012 taught by Professor Charlesg.sodini during the Fall '09 term at MIT.

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MIT6_012F09_lec09 - 6.012 - Microelectronic Devices and...

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