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MIT6_012F09_lec12 - 6.012 Microelectronic Devices and...

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0 i D K(v GS – V T with K (W/ α L) µ e 6.012 - Microelectronic Devices and Circuits Lecture 12 - Sub-threshold MOSFET Operation - Outline Announcement Hour exam two: in 2 weeks, Thursday, Nov. 5, 7:30-9:30 pm ALSO: sign up for an iLab account!! Review MOSFET model: gradual channel approximation (Example: n-MOS) for (v GS – V T )/ α 0 v DS (cutoff) K(v GS – V T ) 2 /2 for 0 (v GS – V T )/ α v DS (saturation) α v DS /2) α v DS for 0 v DS (v GS – V T )/ α (linear) * * C ox , V T = V FB – 2 φ p-Si + [2 ε Si qN A (|2 φ p-Si | – v BS )] 1/2 /C ox and α = 1 + [( ε Si qN A /2(|2 φ p-Si | – v BS )] 1/2 /C ox (frequently α 1) The factor α : what it means physically Sub-threshold operation - qualitative explanation Looking back at Lecture 10 (Sub-threshold electron charge) Operating an n-channel MOSFET as a lateral npn BJT The sub-threshold MOSFET gate-controlled lateral BJT Why we care and need to quantify these observations Quantitative sub-threshold modeling i D,sub-threshold ( φ (0) ), then i D,s-t ( v GS , v DS ) [with v BS = 0] Stepping back and looking at the equations Clif Fonstad, 10/22/09 Lecture 12 - Slide 1
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Final comments on α The Gradual Channel result ignoring α and valid for is: i G ( v GS , v DS , v BS ) = 0, i B ( v GS , v DS , v BS ) = 0, and i D ( v GS , v DS , v BS ) = 0 for v GS " V T ( v BS ) [ ] < 0 < v DS K 2 v GS " V T ( v BS ) [ ] 2 for 0 < v GS " V T ( v BS ) [ ] < v DS K v GS " V T ( v BS ) " v DS 2 # $ % & ( v DS for 0 < v DS < v GS " V T ( v BS ) [ ] with K ) W L μ e C ox * and C ox * ) * ox t ox v BS " 0, and v DS # 0 We noted last lecture that these simple expressions without α are easy to remember, and refining them to include α involves easy to remember substitutions: v DS " # v DS L " # L K " K # What we haven't done yet is to look at α itself, and ask what it means. What is it physically? " # 1 + 1 C ox * $ Si qN A 2 2 % p & Si & v BS [ ] = C ox * + $ Si qN A 2 $ Si 2 % p & Si & v BS [ ] C ox * 1/x DT (V BS ) G ε ox ε ox /t ox ε Si = 1 + " Si x DT " ox t ox = 1 + " Si " ox t ox x DT = 1 + C DT * C ox * = C DT * C GB * ε Si /x DT B Clif Fonstad, 10/22/09 Lecture 12 - Slide 2 Look back at Lec. 10.
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Foil 7 from Lecture 10 MOS Capacitors: the gate charge as v GB is varied Clif Fonstad, 10/22/09 Lecture 12 - Slide 3 v GB [V] V T V FB q G * [coul/cm 2 ] qN AP X DT q G " = C ox " v GB # V T ( ) + qN AP X DT Inversion Layer Charge q G " ( v GB ) = C ox " v GB # V FB ( ) for v GB $ V FB % Si qN A C ox " 1 + 2 C ox " 2 v GB # V FB ( ) % Si qN A # 1 & ( ( ) * + + for V FB $ v GB $ V T C ox " v GB # V T ( ) + qN A X DT for V T $ v GB , - . . / . . The charge expressions: q G " = # Si qN A C ox " 1 + 2 C ox " 2 v GB $ V FB ( ) # Si qN A $ 1 % & ( ) * * Depletion Region Charge q G " = C ox " v GB # V FB ( ) Accumulation Layer Charge C ox " # $ ox t ox
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Foil 8 from Lecture 10 MOS Capacitors: How good is all this modeling? How can we know? Poisson's Equation in MOS As we argued when starting, J h and J e are zero in steady state so the carrier populations are in equilibrium with the potential barriers, φ (x), as they are in thermal equilibrium, and we have: n ( x ) = n i e q " ( x ) kT and p ( x ) = n i e # q " ( x ) kT Once again this means we can find φ (x), and then n(x) and p(x), by solving Poisson's equation: d 2 " ( x ) dx 2 = # q $ n i e # q " ( x )/ kT # e q " ( x )/ kT ( ) + N d ( x ) # N a ( x ) [ ] This version is only valid, however, when | φ (x)| - φ p .
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