MIT6_012F09_lec13

MIT6_012F09_lec13 - 6.012 - Microelectronic Devices and...

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Unformatted text preview: 6.012 - Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline • Announcements Exam Two - Coming next week, Nov. 5, 7:30-9:30 p.m. • Review - Sub-threshold operation of MOSFETs • Review - Large signal models, w. charge stores p-n diode, BJT, MOSFET (sub-threshold and strong inversion) • Small signal models; linear equivalent circuits General two, three, and four terminal devices pn diodes: Linearizing the exponential diode Adding linearized charge stores BJTs: Linearizing the F.A.R. β-model Adding linearized charge stores MOSFETs: Linearized strong inversion model Linearized sub-threshold model Adding linearized charge stores Clif Fonstad, 10/27/09 Lecture 13 - Slide 1 Sub-threshold Operation of MOSFETs, cont. - The barrier at the n+-p junction is lowered near the oxide-Si interface for any vGS > VFB. - The barrier is lowered by φ(x) - φp for 0 < x < xD. (This is the effective vBE on the lateral BJT between x and x + dx.) -tox S VFB < vGS < VT G 0 vDS > 0 φ(0,y) D φn++ vDS Injection xD n+ -φ p φ(x) n+ p tn+ x Plot vs y at fixed x, 0 < x < xD. vBS = 0 0 φ(x) B L y - The barrier lowering vGS (effective forward bias) (1) is controlled by vGS, and (2) decreases quickly with x. vBE,eff(x) = [φ(x)− φp] Clif Fonstad, 10/27/09 - φp φm -tox φn+ y φ(x)-φp L 0 φp Plot vs x at fixed y, 0 < y < L. φ(0) x xd φp Injection occurs over this range, but is largest near x = 0. Lecture 13 - Slide 2 Sub-threshold Operation of MOSFETs, cont. - To calculate iD, we first find the current in each dx thick slab: G VFB < vGS < VT S vDS > 0 D -tox 0 x x+dx n+ n+ p xD vBS = 0 y x 0 n ' ( x, 0) = n i (e q" ( x ,vGS ) / kT # 1) $ n ie q" ( x ,vGS ) / kT diD ( x ) = q De Clif ! Fonstad, 10/27/09 L n ' ( x, L) " n ' ( x, 0) e# qv DS / kT n ' ( x, 0) " n ' ( x, L) W W dx # De q n i (1 " e" qv DS / kT ) ) e q$ ( x,vGS ) / kT dx L L ! Lecture 13 - Slide 3 Sub-threshold Operation of MOSFETs, cont. - Integrating this from x = 0 to x = xD using the approximate value for the integral derived in Lecture 9, and approximating the relationship between Δφ(0) and ΔvGS as linear, i.e. Δφ(0) ≈ ΔvGS/n, we arrived at: 2 $ kT ' W * iD, s"t ( vGS ,vDS ,0) # µ e Cox & ) [n " 1] e q{ vGS "VT } n kT (1 " e "qvDS / kT ) L %q( & * ( 1 #SiqN A ( n " '1 + * + =( Cox 2[$2% p ] ( ) , Variations on this form: It is common to see iD,s-t written using the factors K and γ we defined earlier, and with kT/q replaced by Vt, the thermal voltage, and [n -1] ! replaced in the pre-factor. Written this way, we have: where ! iD ,s" t (vGS , v DS , 0) # K Vt with $ 2 2 ["2% ] e{ vGS "VT } nVt (1 " e " v DS / Vt ) p ( * 2$SiqN A W * "# , K # µe Cox , n (v BS ) % )1 + * Cox L *2 + Clif Fonstad, 10/27/09 ! , * [&2' p & v BS ] * Lecture 13 . " - Slide 4 Sub-threshold Output Characteristic - We plot a family of iD vs vDS curves with (vGS - VT) as the family variable, after first defining the sub-threshold diode saturation current, IS,s-t: $ IS ,s" t # K Vt2 = K Vt2 [ n " 1] 2 ["2% p ] log iD,s-t 10-1 IS,s-t ! (vGS-VT) = -0.12xn Volts 10-2 IS,s-t 10-3 10-4 (vGS-VT) = -0.06xn Volts (vGS-VT) = -0.18xn Volts IS,s-t (vGS-VT) = -0.24xn Volts IS,s-t vDS iD ,s" t (vGS , v DS , 0) # IS ,s" t e{ Clif Fonstad, 10/27/09 vGS "VT } n Vt (1 " e " v DS / Vt ) Lecture 13 - Slide 5 Large Signal Model for MOSFET Operating Sub-threshold - The large signal model for a MOSFET operating in the weak inversion or sub-threshold region looks the same model as that for a device operating in strong inversion (vGS > VT) EXCEPT there is a different equation relating iD to vGS, vDS, and vBS: We will limit our model to D vGS " VT , v DS > 3Vt and v BS = 0. iD ! iD (vGS , vDS ) G iG (= 0) iG ,s" t (vGS , v DS , v BS ) = 0 S,B iD ,s" t (vGS , v DS , 0) # IS ,s" t ! " $v DS ) e{ (1 Clif Fonstad, 10/27/09 ! Early effect vGS "VTo } n Vt (1 " e " v DS / Vt ) ≈ 1 for vDS > 3 Vt Lecture 13 - Slide 6 Large signal models with charge stores: A p-n diode: qAB IBS qAB: Excess carriers on p-side plus excess carriers on n-side plus junction depletion charge. B qBC C BJT: npn (in F.A.R.) iB’ B MOSFET: n-channel qBE: Excess carriers in base plus E-B junction depletion charge qBC: C-B junction depletion charge IBS E qBE D qDB qG iD G S Clif Fonstad, 10/27/09 !FiB’ qG: Gate charge; a function of vGS, B vDS, and vBS. qDB: D-B junction depletion charge qSB: S-B junction depletion charge qSB Lecture 13 - Slide 7 Signal notation: A transistor circuit, whether digital or analog, is typically connected to several DC power supplies that establish the desired DC "bias" currents and voltages throughout it. It also typically has one or more time varying input signals that result in time varying currents and voltages (one of which is the desired output of the circuit) being added to the DC bias currents and voltages. Each voltage and current in such a circuit thus has a DC bias portion and a signal portion, which add to make the total. We use the following notation to identify these components and the total: iA ( t ) = IA + ia ( t ) v AB ( t ) = VAB + v ab ( t ) Total: lower-case letter and uppercase subscript. ! Clif Fonstad, 10/27/09 Signal: lower-case Bias: upper-case letter and subscript. letter and subscript. Lecture 13 - Slide 8 DC Bias Values: To construct linear amplifiers and other linear signal processing circuits from non-linear electronic devices we must use regions in the non-linear characteristics that are locally linear over useful current and voltage ranges, and operate there. To accomplish this we must design the circuit so that the DC voltages and currents throughout it "bias" all the devices in the circuit into their desired regions, e.g. yield the proper bias currents and voltages: IA , IB , IC , ID , etc. and VAG , VBG , VCG , VDG , etc. This design is done with the signal inputs set to zero and using the large signal static device models we have developed for !the non-linear devices we studied: diodes, BJTs, MOSFETs. Working with these models to get the bias values, though not onerous, can be tedious. It is not something we want to have to do to find voltages and currents when the signal inputs are applied. Instead we use linear equivalent circuits . Clif Fonstad, 10/27/09 Lecture 13 - Slide 9 Linear equivalent circuits: After biasing each non-linear devices at the proper point the signal currents and voltages throughout the circuit will be linearly related for small enough input signals. To calculate how they are related, we make use of the linear equivalent circuit (LEC) of our circuit. The LEC of any circuit is a combination of linear circuit elements (resistors, capacitors, inductors, and dependent sources) that correctly models and predicts the first-order changes in the currents and voltages throughout the circuit when the input signals change. A circuit model that represents the proper first order linear relationships between the signal currents and voltages in a non-linear device is call an LEC for that device. Our next objective is to develop LECs for each of the nonlinear devices we have studied: diodes, BJTs biased in their forward active region (FAR), and MOSFETs biased in their sub-threshold and strong inversion FARs. Clif Fonstad, 10/27/09 Lecture 13 - Slide 10 Creating a linear equivalent circuit, LEC: Consider a device with three terminals, X, Y, and Z: qX(vXZ , vXY) qY(vYZ, vYX) X Y iX(vXZ , vYZ) iY(vXZ , vYZ) Z Suppose, as is our situation with the large signal device models we have developed in 6.012, that we have expressions for the currents into terminals X and Y in terms of the voltages vXZ and vYZ: iX (v XZ , vYZ ) and iY (v XZ , vYZ ) and that we similarly have expressions for the charge stores associated with terminals X and Y: ! qX (v XZ , vYZ ) and qY (v XZ , vYZ ) Clif Fonstad, 10/27/09 Lecture 13 - Slide 11 ! Creating an LEC, cont.: We begin with our static model expressions for the terminal characteristics, and write a Taylor's series expansion of them about a bias point, Q, defined as a specific set of vXZ and vYZ that we write, using our notation, as VXZ and VYZ For example, for the current into terminal X we have: "iX "iX 1 " 2iX iX (v XZ , vYZ ) = iX (VXZ ,VYZ ) + (v XZ # VXZ ) + (vYZ # VYZ ) + (v XZ # VXZ ) 2 2 "v XZ Q "vYZ Q 2 "v XZ Q 1 " 2iX 1 " 2iX 2 + (vYZ # VYZ ) + (v XZ # VXZ )(vYZ # VYZ ) + even higher order terms 2 2 "vYZ Q 2 "v XZ "vYZ Q For sufficiently small* (vXZ-VXZ) and (vYZ-VYZ), the second and higher order terms are negligible, and we have: iX (v XZ , vYZ ) " iX (VXZ ,VYZ ) + iX (VXZ ,VYZ ) = IX (VXZ ,VYZ ) #iX #i (v XZ $ VXZ ) + X (vYZ $ VYZ ) #v XZ Q #vYZ Q [v XZ " VXZ ] # v xz [vYZ " VYZ ] # v yz Clif Fonstad, 10/27/09 Lecture 13 - Slide 12 * What is "sufficiently small" is determined by the magnitude of the higher order derivatives. ! ! ! Creating an LEC, cont.: So far we have: i (v , v ) " I (V ,V ) # $iX v + $iX v X XZ YZ X XZ YZ xz yz $v XZ Q $vYZ Q Next we define: [iX " IX ] # ix "iX "v XZ ! # gi Q "iX "vYZ # gr Q Replacing the partial derivatives with the conductances we have defined, gives us our working form of the linear equation relating ! the incremental variables: ! ix " giv xz + grv yz Doing the same for iY, we arrive at $iY $i go # Y $v XZ Q $vYZ Q A circuit matching these relationships is seen below: i iy xx y + ! v xz gi go v yz gr v yz gfv xz z z Lecture 13 Clif Fonstad, 10/27/09 iy " g f v xz + g! yz ov where g f # where - Slide 13 Creating an LEC, cont.: This linear equivalent circuit is only good at low frequencies: x ix + v xz z iy gi gr v yz y go v yz gfv xz z To handle high frequency signals, we linearize the charge stores' dependencies on voltage also. qX(vXZ , vXY) qY(vYZ, vYX) X Y iX(vXZ , vYZ) iY(vXZ , vYZ) Z Their LECs are linear capacitors: "qX "v XZ Clif Fonstad, 10/27/09 # Cxz Q "qY "vYZ # Cyz Q "qX "v XY # Cxy Q $ "q &= Y & "v YX % ' ) ) Q( Lecture 13 - Slide 14 Creating an LEC, cont.: Adding these to the model yields: ix x + v xz gi z iy Cxy Cxz gr v yz Cyz gfv xz go y v yz z Two important points: #1 - All of the elements in this LEC depend on the bias point, Q: gi = "iX "i "i "i "q "q "q , gr = X , g f = Y , go = Y , Cxz = X , Cxy = X , Cyz = Y "v XZ Q "vYZ Q "v XZ Q "vYZ Q "v XZ Q "v XY Q "vYZ #2 - The device-specific nature of an LEC is manifested in the dependences of the element values on the bias currents and voltages, rather than in the topology of the LEC. Thus, different devices may have LECs that look the same. (For example, the BJ and FET LECs may look similar, but some of the elements depend much differently on the bias point values.) Clif Fonstad, 10/27/09 Lecture 13 - Slide 15 Q Linear equivalent circuit (LEC) for p-n diodes (low f): We begin with the static model for the terminal characteristics: qv kT iD (v AB ) = IS [e AB A " 1] + iD vAB IIBS S Linearizing iD about VAB, which we will denote by Q (for quiescent bias point): ! #i iD (v AB ) " iD (VAB ) + D [v AB $ VAB ] #v AB Q – B We define the equivalent incremental conductance of the diode, gd, #i q q ID a+ gd " D = IS e qV / kT $ ! #v AB Q kT kT id AB and we use our notation to write: ! ID = iD (VAB ), id = [iD " ID ], ending up with ! gd v ab = [v AB " VAB ] id = gd v ab b vab – q ID gd " kT The corresponding LEC is shown at right: Clif Fonstad, 10/27/09 Lecture 13 - Slide 16 ! ! LEC for p-n diodes (high f): At high frequencies we must include the charge store, qAB, and linearize its two components*: qAB = qDP + qQNR , p " side A qAB IBS Depletion layer charge store, qDP, and its linear equivalent capacitance, Cdp: ! qDP (v AB ) = " AqN Ap x p (v AB ) # " A 2q$Si N Ap (% b " v AB ) 'qDP Cdp (VAB ) & 'v AB ! Q Cdf (VAB ) " ! q$Si N Ap =A 2 (% b " VAB ) a Diffusion charge store, qQNR,p-side, and its linear equivalent capacitance, Cdf: qQNR , p " side (v AB ) = ! B Clif Fonstad, 10/27/09 iD [ w p " x p ] 2 De #qQNR , p $ side #v AB gd 2 b q ID [ w p $ x p ] = gd % d kT 2 De 2 = Q Cd with % d " * This discusion assumes an n+-p diode) [w p $ xp] 2 2 De Lecture 13 - Slide 17 Linear equivalent circuit for BJTs in FAR (low f): In the forward active region, our static model says: iB (v BE , vCE ) = IBS [e qv BE kT " 1] iC (v BE , vCE ) = # o [1 + $vCE ] iB (v BE , vCE ) = # o IBS [e qv BE kT " 1][1 + $vCE ] We begin by linearizing iC about Q: "iC "i ic (v be , v ce ) = v be + C v ce = gm v be + gov ce ! "v BE Q "vCE Q We introduced the transconductance, gm, and the output conductance, go, defined as: #i #i ! gm " C go " C #v BE Q #vCE Q Evaluating these partial derivatives using our expression for iC, we find: q qI gm = " o IBS e qV kT [1 + #VCE ] $ C BE ! kT go = " o IBS [e qVBE Clif Fonstad, 10/27/09 kT + 1] # $ # IC kT % IC ( ' or $ * VA ) & Lecture 13 - Slide 18 LEC for BJTs (low f), cont.: Turning next to iB, we note it only depends on vBE so we have: "iB ib (v be ) = v be = g# v be "v BE Q The input conductance, gπ, is defined as: $i g" # B $v BE Q ! (Notice that we do not define gπ as qIB/kT) To evaluate gπ we do not use our expression for iB, but instead use iB = iC/βo: $i 1 $iC g q IC g" # B = = m= ! $v % o $v BE Q % o kT % o BE Q Representing this as a circuit we have: ib ! Clif Fonstad, 10/27/09 b + v be g! e ic + v! - gmv ! (Notice that vbe is also called vπ) go c + v ce e Lecture 13 - Slide 19 LEC for BJTs (high f): qBC To extend the model to high frequency we linearize the charge stores associated with the junctions and add them. The base-collector junction is reverse biased so the charge associated with it, qBC, is the depletion region charge. The corresponding capacitance is labeled Cµ. qBC (v BC ) " # A 2q$Si [% b ,BC # v BC ] N DC ! Cµ (VBC ) " C !FiB’ iB’ B IBS qBE #qBC #v BC =A Q E q$Si N DC 2[% b & VBC ] The base-emitter junction is forward biased and its dominant charge store is the excess charge injected into the base; the base-emitter depletion charge store less important. ! 2 wB, eff De qVBE / kT qBE ( vBE ) " Aqn # 1] " iC ( vBE ) [e N AB wB, eff 2 De 2 i The linear equivalent capacitance is labeled Cπ. Clif Fonstad, 10/27/09 ! Lecture 13 - Slide 20 LEC for BJTs (high f), cont: Cπ can be written in terms of gm and τb: $q C" (VBE ) # BE $v BE Q 2 w B ,eff qIC % = gm & b 2 De kT "b 2 w B ,eff # 2 De Adding Cπ and Cµ to our BJT low frequency LEC we get the full BJT LEC: ! ! ib b + v be g! e + v! - c + v ce e q IC kT g g" = m #F gmv ! go Cµ = A C! gm = go = $ IC ic Cµ q"Si N DC 2[# b $ VBC ] C% = gm & b (= IC VA ) Clif Fonstad, 10/27/09 Lecture 13 - Slide 21 ! LEC for MOSFETs in saturation (low f): In saturation, our static model is: (Recall that α ≈ 1) iG (vGS , v DS , v BS ) = 0 iB (vGS , v DS , v BS ) " 0 2 K iD (vGS , v DS , v BS ) = [vGS $ VT (v BS )] [1 + %(v DS $ VDS,sat )] 2# W * with K & µe Cox and VT = VTo + ' 2( p $ Si $ v BS $ 2( p $ Si L ( ! ) Note that because iG and iB are zero they are already linear, and we can focus on iD. Linearizing iD about Q we have: "iD "iD "iD id (v gs, v ds, v bs ) = v gs + v ds + v bs "vGS Q "v DS Q "v BS Q = gm v gs + gov ds + gmb v bs We have introduced the transconductance, gm, output conductance, go, and substrate transconductance, gmb: #iD #iD #iD ! gm " go " gmb " #vGS Q #v DS Q #v BS Q Clif Fonstad, 10/27/09 Lecture 13 - Slide 22 LEC for MOSFETs in saturation (low f), cont.: A circuit containing all these elements, i.e. the actual LEC, is: ig id g d + + v gs v gmv gs gmb v bs go ds -s s- v bs + ib b Evaluating the conductances in saturation we find: gm " go " #iD #vGS #iD #v DS gmb " Clif Fonstad, 10/27/09 = K [VGS % VT (VBS )] [1 + &VDS ] ' $ = K 2 VGS % VT (VBS )] & ' & ID [ 2$ Q Q #iD #v BS =% Q 2 K ID $ K #V [VGS % VT (VBS )] [1 + &VDS ] T $ #v BS = ( gm Q Lecture 13 - Slide 23 LEC for MOSFETs in saturation (high f): D For the high frequency model we qDB linearize and add the charge qG stores associated with each pair iD of terminals. G B Two, qSB and qDB, are depletion region charge stores associated qSB S with the n+ regions of the source and drain. They are relatively straightforward compared to qG., as we will see below. qSB and qDB contribute two capacitors, Csb and Cdb, to our LEC. The gate charge, qG, depends in general on vGS, vDS, and vGB (= vGS-vBS), but in saturation, qG only depends on vGS and vGB (i.e. vGS and vBS) in our model, adding Cgs and Cgb. When vGS ≥ VT the drain is ideally decoupled from the gate , but in any real device there is fringing capacitance between the gate electrode and the drain diffusion that we must include as Cgd, a parasitic element. Clif Fonstad, 10/27/09 Lecture 13 - Slide 24 LEC for MOSFETs in saturation (high f), cont.: Adding all these capacitors to our LEC yields: ig g + v gs sv bs + ib b id Cgd gmv gs Cgs Csb Cgb gmb v bs d + v ds go -s Cdb We find the following results: #q 2 * * * Cgd = W Cgd , where Cgd is the G-D fringing and overlap Cgs " G = W L Cox #vGS Q 3 capacitance per unit gate length (parasitic) Csb , Cgb , Cdb : depletion capacitances ! ! ! gm " 2 K ID # Clif Fonstad, 10/27/09 ! go " $ ID ! gmb = % gm , where % = & 2 2' p ( VBS Lecture 13 - Slide 25 LEC for MOSFETs in saturation when vbs = 0: A very common situation in many circuits is that there is no signal applied between on the base, i.e. vbs = 0 (even though it may be biased relative to the source, VBS ≠ 0 ). In this case the MOSFET LEC simplifies significantly: ig g + v gs s,b - id Cgd gmv gs Cgs go d + v ds Cdb - s,b The elements that remain retain their original dependences: gm " #qG #vGS 2 K ID # go " $ ID 2 * = W L Cox 3 * * Cgd = W Cgd , where Cgd is the G-D fringing and overlap Q capacitance per unit gate length (parasitic) ! Cdb : depletion capacitance Cgs " Clif Fonstad, 10/27/09 ! ! ! Lecture 13 - Slide 26 ! LEC for Sub-threshold MOSFETs, vBS = 0: Our large signal model for MOSFETs operated in the subthreshold FAR (vDS >> kT/q) and vBS = 0, is: D iD iD (vGS , vDS ) G iG (= 0) iG ,s" t (vGS , v DS , v BS ) = 0 iD ,s" t (vGS , v DS ) # IS ,s" t (1 " $v DS ) e{ GS v S,B "VTo } n Vt ! Like a MOSFET in saturation with vbs = 0, the LEC has only ! two elements, gm and go, but now gm is quite different: #i q qI gm " D = IS ,s$ t (1 $ %VDS )e q (V $V ) nkT = D #vGS Q nkT nkT GS #i go " D #v DS Clif Fonstad, 10/27/09 ! = % IS ,s$ t e Q q (VGS $Vto ) nkT & % ID to ' ID * )or & , VA + ( Lecture 13 - Slide 27 LEC for Sub-threshold MOSFETs, vBS = 0, cont.: The LEC for MOSFETs in sub-threshold FAR (vDS >> kT/q) and vBS = 0, is: ig g + v gs s,b - id gmv gs gm = q ID nkT go d + v ds - s,b go " # ID D The charge store qDB is the same as qDB in a MOSFETs operated ! in strong inversion, but gG is not. gG is the gate capacitance in depletion (VFB < vGB < VT), so it is smaller in sub-threshold. qDB qG iD G S,B Clif Fonstad, 10/27/09 Lecture 13 - Slide 28 LEC for Sub-threshold MOSFETs, vBS = 0, cont.: Adding the linear capacitors corresponding to the charge stores we have: ig g + v gs s,b #q Cgs " G #vGS gmv gs Cgs =W L C Q id Cgd $ ox go $ 2Cox2 (VGS % VFB ) 1+ &SiqN A d + v ds Cdb s,b * See Lecture 9, Slides 7 and 8, for qG and the derivation of Cgs. * * Cgd = W Cgd , where Cgd is the G-D fringing and overlap ! ! ! Cdb : depletion capacitance gm = q ID nkT go " # ID Notice that as before, Cgd is zero in our ideal model. It a parasitic that cannot be avoided and must be included because it limits device ! circuit performance. and Clif Fonstad, 10/27/09 Lecture 13 - Slide 29 Comparing the low frequency LECs: All of our circuit design will be done for operation at "low" frequencies, that is where the charge store capacitances play a negligible role. Thus it is interesting to compare our three transistor LECs when this is true. They all have the same topology, but differ importantly in gi and gm: in iin + v in gi common Bias dependences: gi : gm : go : Clif Fonstad, 10/27/09 ! iout gmv in BJT out + go v out common ST MOS SI MOS q IC " F kT 0 q IC kT q ID n kT $ IC $ ID 0 2K ID # $ ID * We will say more about the significance of these differences when we study amplifier design. ST = sub-threshold SI = strong inversion Lecture 13 - Slide 30 The importance of the bias current: A very important observation is that all of the elements in the three LECs we compared depend on the bias level of the output current, IC, in the case of a BJT, or ID, in the case of a MOSFET: Bias dependences: gi : gm : go : BJT ST MOS SI MOS q IC " F kT 0 q IC kT q ID n kT $ IC $ ID 0 2K ID # $ ID ST = sub-threshold SI = strong inversion The bias circuitry is a key part of any linear amplifier. The ! designer must establish a stable bias point for all the transistors in the amplifier to insure that the gain remains constant and stable. We will study amplifier design and practice beginning with Lecture 17. Clif Fonstad, 10/27/09 Lecture 13 - Slide 31 6.012 - Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Summary • Reminder Exam Two - In ~ 1 wk., Thursday, Nov. 5, 7:30-9:30 p.m. Sub-Threshold Refs - Lecture 12 slides; Sub-threshold write-up • Notation Total = Bias + Signal iA ( t ) = IA + ia ( t ) v AB ( t ) = VAB + v ab ( t ) Large signal model - Design and analysis of bias conditions Linear equivalent circuits - Signal portion design/analysis ! • Small signal models; linear equivalent circuits Everything depends on the bias point - The value of each element in an LEC depends on the bias point (often the bias current). Concentrate for now on low frequency LECs - Full spectrum LECs with capacitors will only be used to find the upper bound on the low frequency range of operation. We won't see them again until Lecture 23. Clif Fonstad, 10/27/09 Lecture 13 - Slide 32 MIT OpenCourseWare http://ocw.mit.edu 6.012 Microelectronic Devices and Circuits Fall 2009 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms. ...
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