MIT6_012F09_lec14

# MIT6_012F09_lec14 - 6.012 - Microelectronic Devices and...

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6.012 - Microelectronic Devices and Circuits Lecture 14 - Digital Circuits: Inverter Basics - Outline Announcements Stellar - Two supplemental readings posted Exam Two - Be the first in your living unit to study for it. Review - Linear Equivalent Circuits Everything depends on the bias; only low frequency for now Digital building blocks - inverters A generic inverter MOS inverter options Digital inverter performance metrics Transfer characteristic: logic levels and noise margins Power dissipation Switching speed Fan-out, fan-in Manufacturability Comparing the MOS options And the winner is…. Clif Fonstad, 10/29/09 Lecture 14 - Slide 1

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Reviewing our LECs: Important points made in Lec. 14 We found LECs for BJTs and MOSFETs in both strong inversion and sub-threshold. When v bs = 0, they all look very similar: g i in common g m v in g o common out i in + - v in + - v out i out C i C m C o Most linear circuits are designed to operate at frequencies where the capacitors look like open circuits. We can thus do our designs neglecting them.* Bias dependences: BJT ST MOS SI MOS g i : qI C " F kT 0 0 g m C kT D nkT 2 K o I D # g o \$ I C I D I D ST = sub-threshold SI = strong inversion The LEC elements all depend on the bias levels. Establishing a known, stable bias point is a key part of linear circuit design. We use our large signal models in this design and analysis. * Only when we want to determine the maximum frequency to which Clif Fonstad, 10/29/09 Lecture 14 - Slide 2 our designs can usefully operate must we include the capacitors.
LECs: Identifying the incremental parameters in the characteristics BJT: v DS i D g m g o Q Inc. v GS v GS = v DS (i D ) 1/2 Inc. |v BS | ! V T Q v CE ln i B , ln i C " Q i B i C I C v CE i C g o Q " Inc. i B I C g m = q I C /kT; g π = β g m with β = di C /di B | Q ; g o = di C /dv CE | Q MOSFET: g m = di D /dv GS | Q ; g mb = η g m with η = -dV T /dv BS | Q ; g o = di D /dv DS | Q Clif Fonstad, 10/29/09 Lecture 14 - Slide 3

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Building Blocks for Digital Circuits: inverters Performance metrics A basic Transfer characteristic inverter Logic levels Noise margins Power dissipation Switching speed Fan-in/Fan-out Manufacturability Logic gates NOR: v IN v OUT Lo (0) Hi (1) Hi (1) Lo (0) Pull- Up V DD + + v OUT v IN Device : on or off Switch : open or closed Pull- Up V DD + + v OUT v A + v B NAND: v A v B v OUT 0 0 1 0 1 1 1 0 1 1 1 0 v A v B v OUT 0 0 1 0 1 0 1 0 0 1 1 0 Pull- Up V DD + + v OUT v A + v B Pull- Up V DD Pull- Up Flip-flop Clif Fonstad, 10/29/09 Lecture 14 - Slide 4 Memory cell
Pull- Up V DD + + i PU v OUT v IN i PD Node equation: i PD = i PU i PD = 0 when v IN < V T , PD K PD v IN " V T , PD ( ) 2 2 when 0 < v IN " V T , PD [ ] < v OUT K PD v IN " V T , PD " v OUT 2 ( ) v OUT when 0 < v OUT < v IN " V T , PD [ ] # \$ % % % % & % % % % i PU : Depends on the specific pull-up device used. V DD V IN V OUT Inverter metrics: Transfer characteristic * Note: We can say i PD is zero for the purpose of calculating a transfer characteristic. For power we may want to use: * i PD , off = I S , s " t e " V T nV t For simplicity: α = 1, λ = 0 The transfer characteristic, v OUT vs v IN , is found applying the large signal models at this node Clif Fonstad, 10/29/09

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## This note was uploaded on 11/07/2011 for the course COMPUTERSC 6.012 taught by Professor Charlesg.sodini during the Fall '09 term at MIT.

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MIT6_012F09_lec14 - 6.012 - Microelectronic Devices and...

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