{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}


MIT6_012F09_lec14_inverter - 6.012 Microelectronic Devices...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
6.012 - Microelectronic Devices and Circuits – Fall 2009 Inverter Analysis and Design The inverter stage is a basic building block for digital logic circuits and memory cells. A generic inverter stage is illustrated below on the left. It consists of two devices, a pull-up device, which is typically either a bipolar junction transistor or an enhancement mode field effect transistor, and a pull-down device, which might be another transistor, or a resistor, current source, diode, etc. The stage load which is shown in the figure represents the input resistance of the following stage, which is typically a stage (or n stages) just like the original stage. i SL ( v OUT ) [ = n i IN (v OUT )] i IN ( v IN ) + - v IN + - v OUT Pull Up Pull Down Stage Load + V DD i PU ( v IN, v OUT) i PD ( v IN, v OUT ) + - v IN + - v OUT Pull Up Pull Down Stage Load + V DD (a) A generic inverter stage (b) The static currents to calculate v OUT (v IN) An important piece of information about an inverter stage is its static transfer characteristic, v OUT (v IN ). To calculate this characteristic we sum the currents into the output node of the inverter, as is illustrated above on the right. With all of these currents written as functions of v IN and v OUT , this sum yields the desired relationship: i PU (v IN , v OUT ) = i PD (v IN , v OUT ) + i SL (v OUT ) As an example, consider the MOSFET inverter circuit shown at the top of the next page with an n-channel MOSFET pull-down and a resistor pull-up. The MOSFET is characterized by its K-value and by its threshold voltage, V T (we will assume for simplicity that α is 1). To analyze this circuit we not first that with a MOSFET pull- down, the static input current is zero and if the stage output is connected to the input of a similar stage, the static stage load current will also be zero, and the equation above is simply i PU = i PD . With a resistor pull-up, the pull-up current, i PU , is (V DD - v OUT )/R and the pull-down current, i PD , is the MOSFET drain current. This current depends on the gate-to-source voltage, v GS , which is the same as v IN , and the drain-to-source voltage, v DS , which is the same as v OUT . With v IN less than V T , the pull-down current is zero and v OUT is V DD . As v IN increases past V T , v OUT will initially be larger than 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
(v IN - V T ), and the device will be in saturation so that i PD will be K(v IN - V T ) 2 /2. v OUT is found by setting i PD equal to i PU : i PU = i PD + - v IN + - v OUT + V DD R V T , K i IN = 0 i SL = 0 i PU = ( V - v OUT )/R i PD = 0 if ( v IN - V T ) < 0 < v OUT = K( v IN - V T ) ^2 /2 if 0 < ( v IN - V T ) < v OUT = K( v IN - V T - v OUT /2) v OUT if 0 < v OUT < ( v IN - V T ) A MOSFET inverter with an n-channel MOSFET pull-down and resistor pull-up.
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page1 / 7

MIT6_012F09_lec14_inverter - 6.012 Microelectronic Devices...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon bookmark
Ask a homework question - tutors are online