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Unformatted text preview: 6.012  Microelectronic Devices and Circuits Lecture 15  Digital Circuits: CMOS  Outline • Announcements
• One supplemental reading on Stellar Exam 2  Thursday night, Nov. 5, 7:309:30 Review  Inverter performance metrics
Transfer characteristic: logic levels and noise margins Power: Pave, static + Pave, dynamic (= IONVDD/2 + f CLVDD 2 ) Switching speed: charge thru pullup, discharge thru pulldown
If can model load as linear C: dvOUT/dt = iCH(vOUT)/CL; = iDCH(vOUT)/CL
If can say iCH, iDCH constant: τHILO = CL(VHIVLO)/ICH ; τHILO = CL(VHIVLO)/IDCH Fanout, fanin
Manufacturability (often only 10 to 90% swings) • CMOS
Transfer characteristic Gate delay expressions Power and speedpower product • Velocity Saturation
General comments Impact on MOSFET and Inverter Characteristics Clif Fonstad, 11/3/09 Lecture 15  Slide 1 V OUT V DD Transfer characteristic V HI Node equation: iPD = iPU
0
for v
IN < VT,PD
iPD = KPD(vINVT,PD)2/2 for vINVT,PD < vOUT KPD(vINVT,PD vOUT/2) vOUT f orv V
IN T,PD > vOUT Gives us: VHI and VLO NML and NMH Clif Fonstad, 11/3/09 VM vOUT
V LO
– V IN
NML V DD General approach: Bigger current
→ faster vOUT change iPD + V LO V 1L V M V 1H Switching transients dvout/dt ≈ iCL/CL iPU +
vIN
– iPU: Depends on the device used The load, CL, is a nonlinear charge store, but for MOSFETs it is fairly linear and it is useful to think linear: PullUp PullUp N
V DD MH PullUp i iPU V HI PU iDischarge
+
+
HI to LO – OFF LO
to
HI – Charging cycle:
iCharge = iPU CL + ON +
LO to HI – iPD HI
to
LO CL – Discharging cycle:
iDischarge = iPD – iPU Lecture 15  Slide 2 V DD MOS inverters: 5 pullup
choices PullUp RL
Resistor pullup +
v OUT +
v IN
– Generic
inverter V DD + CL +
v IN
– – V DD V DD v OUT
– V DD V DD V GG
(>>V DD ) +
+
v IN
– v OUT
– +
+
v IN
– v OUT nchannel, emode pullup
VDD on gate
VGG on gate
Clif Fonstad, 11/3/09
* Known as PMOS when made with pchannel. – +
v IN
– + v OUT +
v IN v OUT – – – + nchannel, dmode
pullup (NMOS) Active pchannel
pullup (CMOS)** Lecture 15  Slide 3
** Notice that CMOS has a larger (~3x) input capacitance. Switching transients: summary of charge/discharge currents
V DD Resistor and Emode pullup
(VGG on gate) iPU = iCharge V DD RL V GG
(>>V DD ) +
+
v IN
– iPD = iDischarge + iPU + v OUT +
v IN
– – ION
iCharge v OUT iDischarge ION – v OUT v OUT V DD
iPU = iCharge V DD iPD = iDischarge Emode pullup (VDD on gate) ION +
+
v IN
– iDischarge ION
iCharge v OUT
– v OUT v OUT V DD
iPU = iCharge V DD iPD = iDischarge Dmode pullup V DD
+ iPU iDischarge (called "NMOS") + ION ION
iCharge v OUT +
v IN
– – v OUT iPU = iCharge CMOS
v OUT – iPD = iDischarge iCharge + +
v IN v OUT V DD V DD Clif Fonstad, 11/3/09 V DD
+ iPU – iDischarge
v OUT I
ON ION
ION = 0 V DD
+ iPU V DD • Comparisons made with same pulldown MOSFET, VHI, and ION. v OUT
V DD
Lecture 15  Slide 4 CMOS: transfer characteristic calculation V DD vOUT vOUT vSGp =VTp vGSn= V Tn V DD V DD
Qn
off Qp
+
v IN Qn vDSn = vGSn V Tn Qn : + vSGp = vSDp V Tp Qp : Qp
off Qn lin. v OUT – V Tp  –
vOUT
vGSn =V Tn vSDp = vSGpV Tp II
III
IV V Tn vIN vSGp =VTp vDSn = vGSn V Tn V Tp (V DD +V Tp ) V DD V DD V DD
I Qp sat. vIN V Tn Clif Fonstad, 11/3/09 Qp lin. Qn sat. V (V DD +V Tp ) V DD vIN Transistor operating condition
in each region:
Region
Qn
Qp
I
II
III
IV
V cutoff
saturation
saturation
linear
linear linear
linear
saturation
saturation
cutoff
Lecture 15  Slide 5 CMOS: transfer characteristic calculation, cont. Region I: #
(VDD " vOUT )& V " v
iDn = 0 and iDp = K p %VDD " v IN " VTp "
(( DD OUT )
2
$
'
so iDn = iDp ) vOUT = VDD Region II: ! #
vOUT &
iDn = K n %v IN " VTn "
v
$
' OUT
2(
so iDn = iDp ) vOUT = 0
V DD and iDp = 0
vOUT
vGSn =V Tn vSGp =VTp V DD
I ! vSDp = vSGpV Tp II Qp vDSn = vGSn V Tn
III +
v IN
– Qn +
v OUT V Tp  IV – V Tn
Clif Fonstad, 11/3/09 V (V DD V Tp ) V DD vIN Lecture 15  Slide 6 CMOS: transfer characteristic calculation, cont.
Region III:
iDn = Kn
2
[ v IN " VTn ]
2 so iDn = iDp # v IN [ 2
Kp
V DD v IN " VTp
2
VDD " VTp + VTn K n K p
=
. To achieve symmetry we make
1 + Kn K p and iDp == K n = K p , and VTp = VTn . With this : v IN =
V DD ! V DD Qp
+
v IN Qn – + V DD /2+V Tp  I vSDp = vSGpV Tp II
III vDSn = vGSn V Tn IV V v OUT
– V DD /2V Tn
V Tp  Regions II and IV:
Parabolic segments connecting the three straight segments. Clif Fonstad, 11/3/09 VDD
V
V
and DD " VTn $ vOUT $ DD + VTp
2
2
2
vOUT
vSGp =VTp
vGSn =V Tn V Tn V DD /2 (V DD  V DD
V Tp ) vIN Lecture 15  Slide 7 CMOS: transfer characteristic calculation, cont. Complete characteristic so far: V DD V DD
(V DD/2V Tp) Kp
V Tp
+
v IN
– V OUT + Kn
V Tn v OUT V DD/2
(V DD/2V Tn)
V Tp – V Tn V DD/2 (V DD + V DD
V Tp ) V IN NOTE: We design CMOS inverters to have Kn = Kp and VTn = VTp
to obtain the optimum symmetrical characteristic.
Clif Fonstad, 11/3/09 Lecture 15  Slide 8 CMOS: transfer characteristic calculation, cont.
vOUT Our calculation says that the
transfer characteristic is
vertical in Region III. V DD We know it must have some
slope, but what is it?
To see, calculate the small
signal gain about the bias
point: VIN = VOUT = VDD/2 V Tp
V Tn Begin with the small signal model:
V DD
Qp K p !p
V Tp sp V DD/2 (V DD  V DD
V Tp ) vIN
sp  v gsp = v in
gp + gmp v gsp gop
dp gn +
V DD/2+v in Qn –
Clif Fonstad, 11/3/09 +
+
Kn !n V DD/2+v out v in
V Tn
– +
v gsn = v in
sn dn +
v out gmnv gsn gon sn
Lecture 15  Slide 9 CMOS: transfer characteristic calculation, cont. Redrawing the circuit we get gn ,gp
+
v in +
v gsn =v gsp  dn ,dp  gmnv in gmp v in gon gop sn ,sp +
v out  s ,s
np from which we see immediately #v
Av " OUT
#v IN Q [gmn + gmp ]
v out
=
=$
v in
[gon + gop ] In Lecture 13 we learned how to write the conductances in terms
of the bias point as gmn = ! 2K n IDn , gmp = 2K p IDp = gmn , gon = "n IDn , gop = " p IDp = " p IDn which will enable us to express the gain in terms of the bias
point, IDn (= IDp), and MOSFET parameters ! Av "
Clif Fonstad, 11/3/09 #vOUT
#v IN =$
Q 2 2K n IDn
2 2K n
=$
[%n + % p ]IDn [%n + % p ] IDn Lecture 15  Slide 10 CMOS: transfer characteristic calculation, cont.
vOUT Returning to the transfer characteristic,
we see that the slope in Region III is
not infinite, but is instead: #v
Av " OUT
#v IN [g
=$
[g mn Q on + gmp ] V DD V DD/2 + gop ] V Tp vOUT ! Final comment: A quick and
easy way to approximate the
transfer characteristic of a
CMOS gate is to simply draw
the three straight line portions
in Regions I, III, and V: Av V Tn V DD V DD/2 Av V DD/2
Clif Fonstad, 11/3/09 V DD/2 (V DD  V DD
V Tp ) vIN vIN
V DD
Lecture 15  Slide 11 CMOS: switching speed; minimum cycle time
The load capacitance: CL
• Assume to be linear
• Is proportional to MOSFET gate area
• In channel: µe = 2µh so to have Kn = Kp we must have Wp/Lp = 2Wn/Ln
Typically Ln = Lp = Lmin and Wn = Wmin, so we also have Wp = 2Wmin *
*
*
CL " n [W n Ln + W p L p ]Cox = n [W min Lmin + 2W min Lmin ]Cox = 3nW min Lmin Cox Charging cycle: vIN: HI to LO; Qn off, Qp on; vOUT: LO to HI ! • Assume charged by constant iD,sat iCh arg e = "iDp [ Kp
#
VDD " VTp
2 2 = Kn
2
[VDD " VTn ]
2 Qp qCh arg e = CLVDD $ Ch arg e qCh arg e
2CLVDD
=
=
iCh arg e K n [VDD " VTn ] 2
= Clif Fonstad, 11/3/09 *
6 nW min Lmin CoxVDD W min
2
*
µe Cox [VDD " VTn ]
Lmin +
v IN 6 nL2 VDD
min
=
2
µe [VDD " VTn ] V DD – +
Qn CL v OUT
– Lecture 15  Slide 12 CMOS: switching speed; minimum cycle time, cont. Discharging cycle: vIN: LO to HI; Qn on, Qp off; vOUT: HI to LO
• Assume discharged by constant iD,sat
V DD
Kn
2
iDisch arg e = iDn "
[VDD # VTn ]
2
Qp
qDisch arg e = CLVDD $ Disch arg e qDisch arg e
2CLVDD
=
=
iDisch arg e K n [VDD # VTn ] 2 = *
6 nW min Lmin CoxVDD W min
2
*
µe Cox [VDD # VTn ]
Lmin Minimum cycle time: = +
v IN 6 nL2 VDD
min µe [VDD # VTn ] vIN: LO to HI to LO; " Min.Cycle = " Ch arg e + " Disch arg e !
Clif Fonstad, 11/3/09 ! – +
Qn CL v OUT
– 2 vOUT: HI to LO to HI 12 nL2 VDD
min
=
2
µe [VDD # VTn ]
Lecture 15  Slide 13 CMOS: switching speed; minimum cycle time, cont. Discharging and Charging times: What do the expressions tell us? We have " Min Cycle 12 nL2 VDD
min
=
2
µe [VDD # VTn ] This can be written as: ! " Min Cycle = 12 nVDD
Lmin
$
(VDD # VTn ) µe (VDD # VTn ) Lmin The last term is the channel transit time: ! Lmin
Lmin
L
=
= min = $ Ch Transit
µe (VDD " VTn ) Lmin
µe #Ch
se,Ch Thus the gate delay is a multiple of the channel transit time: !
Clif Fonstad, 11/3/09 ! " Min Cycle = 12 nVDD
" Channel Transit = n ' " Channel Transit
(VDD # VTn )
Lecture 15  Slide 14 CMOS: power dissipation  total and per unit area
Average power dissipation
All dynamic
2
*
2
Pdyn ,ave = E Dissipated per cycle f = CLVDD = 3nW min Lmin CoxVDD f Power at maximum data rate
Maximum f will be 1/τGate Delay Min. ! Pdyn @ f max = *
ox 2
DD 3nW min Lmin C V
" Min .Cycle
= µe [VDD $ VTn ]
*
2
= 3nW min Lmin CoxVDD #
12 nL2 VDD
min 2 1 W min
2
*
µe CoxVDD [VDD $ VTn ]
4 Lmin Power density at maximum data rate
Assume that the area per inverter is proportional to WminLmin ! PDdyn @ f max =
Clif Fonstad, 11/3/09 ! Pdyn @ f max
InverterArea " Pdyn @ f max
W min Lmin *
µe CoxVDD [VDD # VTn ]
=
L2
min 2 Lecture 15  Slide 15 CMOS: design for high speed Maximum data rate
Proportional to 1/τMin Cycle " Min.Cycle = " Ch arg e + " Disch arg e = 12 nL2 VDD
min µe [VDD # VTn ] 2 Implies we should reduce Lmin and increase VDD.
Note: As we reduce Lmin we must also reduce tox, but tox doesn't
enter directly in fmax so it doesn't impact us here !
Power density at maximum data rate Assume that the area per inverter is proportional to WminLmin PDdyn @ f max " !
Clif Fonstad, 11/3/09 Pdyn @ f max
W min Lmin µe#oxVDD [VDD $ VTn ]
=
t ox L2
min 2 Shows us that PD increases very quickly as we reduce Lmin
unless we also reduce VDD (which will also reduce fmax).
Note: Now tox does appear in the expression, so the rate of increase
with decreasing Lmin is even greater because tox must be reduced
along with L.
How do we make fmax larger without melting the silicon?
By following CMOS scaling rules  the topic of Lecture 16. Lecture 15  Slide 16 CMOS: velocity saturation
Sanity check
CMOS gate lengths are now under 0.1 µm (100 nm). The electric field
in the channel can be very high: Ey ≥ 104 V/cm when vDS ≥ 0.1 V. Clearly the velocity of the electrons and holes in the channel will
be saturated at even low values of vDS!
What does this mean for the device and inverter characteristics?
Clif Fonstad, 11/3/09 Lecture 15  Slide 17 CMOS: velocity saturation, cont. Models for velocity saturation*
Two useful models are illustrated below. We'll use Model A today. Model A Model B Model A sy ( E y ) = µe E y if E y " E crit
= µe E crit # ssat if E y $ E crit Clif Fonstad, 11/3/09 ! µe E y
sy ( E y ) =
Ey
1+
E crit Model B * See pp 281ff and 307ff in course text. Lecture 15  Slide 18 CMOS: velocity saturation, cont.
Drain current: iD(vGS,vDS,vBS)
With Model A*, the low field iD model, s = µE, holds for increasing vDS
until the velocity of the electrons at some point in the channel
reaches ssat (this will happen at the drain end). When this happens
the current saturates, and does not increase further for larger vDS.
iD EcrL
Clif Fonstad, 11/3/09 vDS
* Model A: sy ( E y ) = µe E y = µe E crit # ssat if E y " E crit if E y $ E crit Lecture 15  Slide 19 CMOS: velocity saturation, cont.
If the channel length, L, is sufficiently small we can simplify the
model even further because the carrier velocity will saturate at
such a small vDS that for vDS ≥ EcritL the inversion layer will be
uniform and all the carriers will be drifting at their saturation
velocity. In this situation (the saturation region) we will have:
*
iD (vGS , v DS , v BS ) " #W qN (vGS , v BS ) ssat = W ssat Cox [vGS # VT (v BS )] ! For smaller vDS, prior to the onset of velocity saturation, the linear
region model we had earlier will hold. The entire characteristic,
neglecting the vDS/2 factor in the linear region expression, is %
0
'
'
*
iD (vGS , v DS , v BS ) " & W ssat Cox [vGS # VT (v BS )]
'W
*
' µe Cox [vGS # VT (v BS )]v DS
(L for
(vGS # VT ) < 0 < v DS
for 0 < (vGS # VT ), $ crit L < v DS
for 0 < (vGS # VT ), v DS < $ crit L Note that the current in saturation increases linearly with (vGS  VT),
rather than as its square like it did then the gate was longer.
Clif Fonstad, 11/3/09 Lecture 15  Slide 20 CMOS: velocity saturation, cont.
This simple model for the output characteristics of a very short
channel MOSFET (plotted below) provides us an easy way to
understand the impact of velocity saturation on MOSFET and
CMOS inverter performance.
iD vDS EcritL Note first that in the forward active region where vDS ≥ EcritL,
the curves in the output family are evenly spaced, indicating
a constant gm:
* gm " #iD #vGS Q = W ssat Cox Clif Fonstad, 11/3/09 Lecture 15  Slide 21 CMOS: velocity saturation, cont. Charge/discharge cycle and gate delay:
The charge and discharge currents, charges, and times are now: *
iDisch arg e = iCh arg e = W min ssat Cox (VDD " VTn ) *
qDisch arg e = qCh arg e = CLVDD = 3W min Lmin CoxVDD # Disch arg e = # Ch arg e *
qDisch arg e
3W min Lmin CoxVDD
3nLminVDD
=
=
=
*
iDisch arg e W min ssat Cox (VDD " VTn ) ssat (VDD " VTn ) CMOS minimum cycle time and power density at fmax: ! " Min.Cycle = " Ch arg e + " Disch arg e = " Min.Cycle #
! ! 6 n LminVDD
ssat [VDD # VTn ] LminVDD
= n ' " ChanTransit
ssat [VDD $ VTn ] Note: " ChanTransit = PDdyn @ f max "
! L
ssat ssat #oxVDD [VDD $ VTn ]
t ox Lmin Lessons: Still gain by reducing L, but not as quickly.
Scaling of both dimensions and voltage is still required.
Channel transit time, Lmin/ssat, still rules!
Clif Fonstad, 11/3/09 ! Lecture 15  Slide 22 MOSFETs: LEC w. velocity saturation Small signal linear equivalent circuit: gm and Cgs change
Cgd g d gm " +
Cgs
v gs
 gmv gs go
s,b s,b #iD
#vGS *
= W ssat Cox
Q *
Cgs = W L Cox One final model observation: Insight on gm
We in general want gm as large as possible. To see another way
!
to think about this is to note that gm can be related to τChTransit:
No velocity
saturation
Full velocity
saturation gm *
#W
'
W L Cox
*
% µe Cox (vGS " VT ) = 2
%
%L
Cgs
L µe (vGS " VT ) %
=$
(*
*
W L Cox
+ Ch Transit
*
%
%
W ssat Cox
=
%
%
L ssat
&
) Cgs is a measure of how much channel charge we are controlling,
and 1/τChtr is a measure of how fast it moves through the device.
We'd like both to be large numbers. ! Clif Fonstad, 11/3/09 Lecture 15  Slide 23 6.012  Microelectronic Devices and Circuits Lecture 15  Digital Circuits: CMOS  Summary V
• CMOS
DD Transfer characteristic: symmetric VLO = 0, VHI = VDD, ION = 0 NML = NMH implies Kn = Kp, VTp = VTn ≡VT Ln = Lp = Lmin, Wp = (µe/µh)Wn + +
v IN
– Gate delay expressions v OUT
– τLOHI = τHILO = 2VDDCL/Kn(VDD  VT)2
Gate delay (GD) = τLOHI + τHILO = 4VDDCL/Kn(VDD  VT)2
If CL = n(WnLn + WpLp)Cox* = 3n WnLminCox*
(Assumes µe = 2µh)
then GD = 12 n Lmin2 VDD/ µn(VDD  VT)2
(Motivation for reducing Lmin) Power and speedpower product
Pave = f CLVDD 2 Pdyn@ fmax ∝ CLVDD2/GD = KnVDD (VDD  VT)2/4 (Motivation for reducing VDD) • Velocity Saturation
Gate delay; Power and speedpower product:
Scales as 1/Lmin, rather than (1/Lmin)2
Clif Fonstad, 11/3/09 Lecture 15  Slide 24 MIT OpenCourseWare
http://ocw.mit.edu 6.012 Microelectronic Devices and Circuits
Fall 2009 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms. ...
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This note was uploaded on 11/07/2011 for the course COMPUTERSC 6.012 taught by Professor Charlesg.sodini during the Fall '09 term at MIT.
 Fall '09
 CharlesG.Sodini

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