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Unformatted text preview: 1 6.012 - Microelectronic Devices and Circuits, Fall 2009 - 10/28/09 Posting CMOS Gate Delays Assume we have a symmetrical CMOS inverter with V Tn = |V Tp | V T and K n = K p . Also assume that both the n- and p-channel devices are minimum gate length devices, so L n = L p = L min , Also assume C o * xn = C o * xp C o * x . Finally, assume e = 2 h , so if we make the p-channel device twice as wide as the n-channel device, we get the desired K equality; i.e., W p = 2 W n , yields K p = W p h C o * xp = 2 W n e C o * xn = K n . L p L n 2 The gate delay of an inverter is the sum of the times it takes the gate to switch from a LO to a HI output, and from a HI to a LO output. To estimate these times for a CMOS gate we first note that during the LO to HI cycle, the load capacitance, C L , is charged from 0 V to V DD , which requires a total charge of C L V DD , through the p- channel device. During much of this cycle the p-channel MOSFET will be in saturation with V GS = -V...
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- Fall '09