Unformatted text preview: 6.012  Microelectronic Devices and Circuits Lecture 16  CMOS scaling; The Roadmap  Outline
• Announcements
PS #9  Will be due next week Friday; no recitation tomorrow. Postings  CMOS scaling (multiple items) Exam Two  Tonight, Nov. 5, 7:309:30 pm • Review  CMOS gate delay and power
Lecture 15 results: Gate Delay = 12 n Lmin2 VDD/ µn(VDD  VT)2
P[email protected] ∝ CLVDD2/GD = KnVDD (VDD  VT)2/4 Velocity Saturation • CMOS scaling rules
Power density issues and challenges Approaches to a solution: Dimension scaling alone Scaling voltages as well • The Road Map; the Future
Size and performance evolution with time How long can it go on? Clif Fonstad, 11/5/09 Lecture 16  Slide 1 CMOS: transfer characteristic Complete characteristic w.o. Early effect:
V OUT
V DD
V DD Kp
V Tp
+
v IN
– (V DD/2V Tp)
+ Kn
V Tn v OUT
– V DD/2
(V DD/2V Tn)
V Tp
V Tn V DD/2 (V DD + V DD
V Tp ) V IN NOTE: We design CMOS inverters to have Kn = Kp and VTn = VTp
to obtain the optimum symmetrical characteristic.
Clif Fonstad, 11/5/09 Lecture 16  Slide 2 CMOS: transfer characteristic calculation, cont.
vOUT We found from an LEC analysis that
the slope in Region III is not infinite,
but is instead: Av " v out #vOUT
=
v in
#v IN [g
=$
[g mn
on V DD/2 Av Q (= VDD / 2,VDD / 2) + gmp ]
+ gop ] V DD V Tp 2 2K n
=$
[%n + % p ] IDn V Tn vOUT V DD/2 (V DD  V DD
V Tp ) vIN V DD ! Quick approximation: An easy
way to sketch the transfer
characteristic of a CMOS gate
is to simply draw the three
straight line portions in
Regions I, III, and V: V DD/2 Av V DD/2
Clif Fonstad, 11/5/09 vIN
V DD
Lecture 16  Slide 3 CMOS: switching speed; minimum cycle time
The load capacitance: CL
• Assume to be linear
• Is proportional to MOSFET gate area
• In channel: µe = 2µh so to have Kn = Kp we must have Wp/Lp = 2Wn/Ln
Typically Ln = Lp = Lmin and Wn = Wmin, so we also have Wp = 2Wmin *
*
*
CL " n [W n Ln + W p L p ]Cox = n [W min Lmin + 2W min Lmin ]Cox = 3nW min Lmin Cox Charging cycle: vIN: HI to LO; Qn off, Qp on; vOUT: LO to HI ! • Assume charged by constant iD,sat iCh arg e = "iDp [ Kp
#
VDD " VTp
2 2 = Kn
2
[VDD " VTn ]
2 Qp qCh arg e = CLVDD $ Ch arg e qCh arg e
2CLVDD
=
=
iCh arg e K n [VDD " VTn ] 2
= Clif Fonstad, 11/5/09 *
6 nW min Lmin CoxVDD W min
2
*
µe Cox [VDD " VTn ]
Lmin +
v IN 6 nL2 VDD
min
=
2
µe [VDD " VTn ] V DD – +
Qn CL v OUT
– Lecture 16  Slide 4 CMOS: switching speed; minimum cycle time, cont. Discharging cycle: vIN: LO to HI; Qn on, Qp off; vOUT: HI to LO
• Assume discharged by constant iD,sat
V DD
Kn
2
iDisch arg e = iDn "
[VDD # VTn ]
2
Qp
qDisch arg e = CLVDD $ Disch arg e qDisch arg e
2CLVDD
=
=
iDisch arg e K n [VDD # VTn ] 2 = *
6 nW min Lmin CoxVDD W min
2
*
µe Cox [VDD # VTn ]
Lmin Minimum cycle time: = +
v IN 6 nL2 VDD
min µe [VDD # VTn ] vIN: LO to HI to LO; " Min.Cycle = " Ch arg e + " Disch arg e !
Clif Fonstad, 11/5/09 ! – +
Qn CL v OUT
– 2 vOUT: HI to LO to HI 12 nL2 VDD
min
=
2
µe [VDD # VTn ]
Lecture 16  Slide 5 CMOS: switching speed; minimum cycle time, cont. Discharging and Charging times: What do the expressions tell us? We have " Min Cycle 12 nL2 VDD
min
=
2
µe [VDD # VTn ] This can be written as: ! " Min Cycle = 12 nVDD
Lmin
$
(VDD # VTn ) µe (VDD # VTn ) Lmin The last term is the channel transit time: ! Lmin
Lmin
L
=
= min = $ Ch Transit
µe (VDD " VTn ) Lmin
µe #Ch
se,Ch Thus the gate delay is a multiple of the channel transit time: !
Clif Fonstad, 11/5/09 ! " Min Cycle = 12 nVDD
" Channel Transit = n ' " Channel Transit
(VDD # VTn )
Lecture 16  Slide 6 CMOS: power dissipation  total and per unit area
Average power dissipation
Only dynamic for now
2
*
2
Pdyn ,ave = E Dissipated per cycle f = CLVDD = 3nW min Lmin CoxVDD f Power at maximum data rate
Maximum f will be 1/τGate Delay Min. ! Pdyn @ f max = *
ox 2
DD 3nW min Lmin C V
" Min .Cycle
= µe [VDD $ VTn ]
*
2
= 3nW min Lmin CoxVDD #
12 nL2 VDD
min 2 1 W min
2
*
µe CoxVDD [VDD $ VTn ]
4 Lmin Power density at maximum data rate
Assume that the area per inverter is proportional to WminLmin ! PDdyn @ f max = Clif Fonstad, 11/5/09 ! [email protected] max
InverterArea " [email protected] max
W min Lmin *
µe CoxVDD [VDD # VTn ]
=
L2
min 2 Lecture 16  Slide 7 CMOS: design for high speed Maximum data rate
Proportional to 1/τMin Cycle " Min.Cycle = " Ch arg e + " Disch arg e = 12 nL2 VDD
min µe [VDD # VTn ] 2 Implies we should reduce Lmin and increase VDD.
Note: As we reduce Lmin we must also reduce tox, but tox doesn't
enter directly in fmax so it doesn't impact us here !
Power density at maximum data rate Assume that the area per inverter is proportional to WminLmin PDdyn @ f max " ! [email protected] max
W min Lmin µe#oxVDD [VDD $ VTn ]
=
t ox L2
min 2 Shows us that PD increases very quickly as we reduce Lmin
unless we also reduce VDD (which will also reduce fmax).
Note: Now tox does appear in the expression, so the rate of increase
with decreasing Lmin is even greater because tox must be reduced
along with L to stay in the gradual channel regime. How do we make fmax larger without melting the silicon?
Clif Fonstad, 11/5/09 By following CMOS scaling rules, the topic of today's lecture. Lecture 16  Slide 8 CMOS: velocity saturation
Sanity check before looking at device scaling
CMOS gate lengths are now under 0.1 µm (100 nm). The electric field
in the channel can be very high: Ey ≥ 104 V/cm when vDS ≥ 0.1 V. Model A
Electrons:
Holes: Clearly the velocity of the electrons and holes in the channel will
be saturated at even low values of vDS!
What does this mean for the device and inverter characteristics?
Clif Fonstad, 11/5/09 Lecture 16  Slide 10 MOS: Output family with velocity saturation iD vDS EcritL
%
0
'
'
*
iD (vGS , v DS , v BS ) " & W ssat Cox [vGS # VT (v BS )]
'W
*
' µe Cox [vGS # VT (v BS )]v DS
(L ! for vGS < VT , 0 < v DS Cutoff for VT < vGS , $ crit L < v DS Saturation for VT < vGS , 0 < v DS < $ crit L Linear This simple model for the output characteristics of a very short
channel MOSFET (plotted above) provides us an easy way to
understand the impact of velocity saturation on MOSFET and
CMOS inverter performance.
Clif Fonstad, 11/5/09 Lecture 16  Slide 11 CMOS: Gate delay and fmax with velocity saturation
Charge/discharge cycle and gate delay:
The charge and discharge currents, charges, and times are now:
*
iDisch arg e = iCh arg e = W min ssat Cox (VDD " VTn )
*
qDisch arg e = qCh arg e = CLVDD = 3W min Lmin CoxVDD # Disch arg e = # Ch arg e *
qDisch arg e
3W min Lmin CoxVDD
3nLminVDD
=
=
=
*
iDisch arg e W min ssat Cox (VDD " VTn ) ssat (VDD " VTn ) CMOS minimum cycle time and power density at fmax: ! " Min.Cycle = " Ch arg e + " Disch arg e = 6 n LminVDD
ssat [VDD # VTn ] Note: " ChanTransit = L
ssat LminVDD
" Min.Cycle #
= n ' " ChanTransit
ssat [VDD $ VTn ]
! ! Lessons: We still benefit from reducing L, but not as quickly.
Channel transit time, Lmin/ssat, is still critical.
Clif Fonstad, 11/5/09 ! Lecture 16  Slide 12 CMOS: Power and power density with velocity saturation
Average power dissipation
All dynamic
2
*
2
Pave = E Dissipated per cycle f = CLVDD = 3nW min Lmin CoxVDD f Power at maximum data rate
Maximum f will be 1/τGate Delay Min.
*
2
!
ssat [VDD $ VTn ]
3nW min Lmin CoxVDD
*
2
Pdyn @ f max =
= 3nW min Lmin CoxVDD #
" Min .Cycle
6 n LminVDD 1
*
= W min ssat CoxVDD [VDD $ VTn ]
2
Power density at maximum data rate
Assume that the area per inverter is proportional to WminLmin ! PDdyn @ f max = [email protected] max
InverterArea " [email protected] max
W min Lmin *
ssat Cox VDD [VDD # VTn ]
=
Lmin Lesson: Again benefit from reducing L, but again not as quickly.
Clif Fonstad, 11/5/09 ! Lecture 16  Slide 13 CMOS: Collected results
Maximum data rate:
No velocity saturation: L2 VDD
min
" Min.Cycle #
2
µe [VDD $ VTn ] With velocity saturation: " Min.Cycle #
! Smaller
is faster LminVDD
ssat [VDD $ VTn ] Power density at maximum data rate:
No velocity saturation: ! PDdyn @ f max µe "ox VDD [VDD # VTn ]
=
t ox L2
min 2 With velocity saturation: !
Clif Fonstad, 11/5/09 PDdyn @ f max ssat "ox VDD [VDD # VTn ]
=
t ox Lmin Smaller also
dissipates
more power
per unit area Lecture 16  Slide 14 ! Scaling Rules  making CMOS faster without melting Si
General idea:
Reduce dimensions by factor 1/s: s > 1 Evaluate impact on speed, power, power density Assume no velocity saturation for now Scaling dimensions alone:
Lmin " Lmin s
W "W s t ox " t ox s NA " s NA This yields "ox
*
*
C=
: Cox # sCox
t ox
*
ox !
and thus ! L2 VDD
min
"#
2:
µe [VDD $ VTn ] *
2
Pdyn = 3nW min Lmin CoxVDD f : W
*
K = µe Cox : K # sK
L " % " s2
Pdyn % sPdyn µe &ox VDD [VDD $ VTn ]
=
: PDdyn @ f max % s3 PDdyn @ f max
t ox L2
min
2 PDdyn @ f max
Clif Fonstad, 11/5/09 ! Scaling dimensions alone can yield melted silicon!! Lecture 16  Slide 15 Scaling Rules, cont.  constant Efield scaling
Observation:
Reducing dimensions alone won't work.
Reduce voltage in concert (constant Efield scaling) Scaling dimensions and voltages by 1/s:
Lmin " Lmin s
W "W s
t ox " t ox s VDD " VDD s
We still have ! *
*
Cox " sCox but now we find !
! VBS " VBS s NA " s NA VT " VT s K " sK L2 VDD
min
"#
2:
µe [VDD $ VTn ] *
2
Pdyn = 3nW min Lmin CoxVDD f : " %" s
Pdyn % Pdyn s2 µ & V [VDD $ VTn ]
= e ox DD 2
: PDdyn @ f max % PDdyn @ f max
t ox Lmin
2 PDdyn @ f max When we scale dimension and voltage we get higher speed and lower power, while holding the power density unchanged. Clif Fonstad, 11/5/09 ! Lecture 16  Slide 16 Scaling Rules, cont.  constant Efield scaling
Threshold voltage:
We've said VT scales, but this merits some discussion*:
t
VT (v BS ) " VFB + 2# p $ Si + ox 2%SiqN A 2# p $ Si + v BS [ %ox Small because with n+poly Si
gate, φm ≈  φp and VFB ≈ 2φp ! Thus: VT (v BS ) " Dominated by vBS if
vBS >> 2φp t ox
ts
2#Si q N A v BS $ ox
2#Si q sN A v BS s $ VT s
#ox
#ox
It works. Subthreshold leakage and static power:
Including VBS, IDoff is: ! ID,off " W
#Si q N A
µe Vt2
L
2 $ 2% p + VBS [ e{ $VT } nVt " W
# qN
µe Vt2 Si A e{$VT } nVt
L
2 VBS Scaling all the factors, we find that IDoff and Pstatic scale poorly! ID,off " s ID,off e ! Clif Fonstad, 11/5/09 ! *$ 1 ' +&1# )VT . nVt
,% s ( / PStatic = VDD ID ,off " PStatic e * We're talking nchannel here, but similar results
are found for the pchannel MOSFETs. ! *$ 1 ' +&1# )VT . nVt
,% s ( / Lecture 16  Slide 17 Scaling Rules, cont.  static power scales badly, but... Static power density's scaling is even worse: ID,off VDD
s ID ,off e( s#1)VT s n Vt VDD s
PDstatic =
"
" s2 e( s#1)VT
W min Lmin
W min Lmin s2 s n Vt PDstatic A typical
VT/nVt is ~10.
If s = √ 2 , the
exponential
factor is ~ e3,
or about 20!
in a chip ! Bottom Line:
Static power
can no longer
be neglected. Figure source:
Intel Web Site Clif Fonstad, 11/5/09 Lecture 16  Slide 18
Reprinted with permission of Intel Corporation. Scaling Rules, cont.  What about velocity saturation? Do the same constant Efield scaling by 1/s:
Lmin " Lmin s
W "W s
t ox " t ox s VDD " VDD s
so ! VBS " VBS s *
*
Cox " sCox NA " s NA VT " VT s K " sK !
Examining our expressions when velocity saturation is
important we find: ! LminVDD
"#
:
ssat [VDD $ VTn ] *
2
Pdyn = 3nW min Lmin CoxVDD f : PDdyn @ f max = " %" s
Pdyn % Pdyn s2 ssat &ox VDD [VDD $ VTn ]
: PDdyn @ f max % PDdyn @ f max
t ox Lmin Amazingly, there is no difference in the scaling behavior of the gate delay, average power, or power density in this case! Note: Velocity saturation is not a factor in ID,off.
Lecture 16
! Clif Fonstad, 11/5/09  Slide 19 An historical scaling example  Inside Intel Parameter 386 486 Pentium Scaling factor, s 1 2 3 Lmin (µm) 1.5 0.75 0.5 W n ( µ m) 10 5 3 tox (nm) 30 15 9 VDD (V) 5 3.3 2.2 V T (V ) 1   Fan out 3 3 3 K (µA/V2) 230 450 600 GD (ps) 840 400 250 fmax (MHz) 29 50 100 Pave/gate (mW) 92 23 10 Density 220 880 2,000 (kgates/cm2 @
Clif Fonstad, 11/5/09 20W/cm2 max.) Sources: Prof. Jesus del Alamo and Intel Lecture 16  Slide 20 An second look inside Intel  a slightly different perspective Parameter 486 Scaling factor, s  1 1.6 2.3 Lmin (µm) 1.0 0.8 0.5 0.35  111 44 21 Die size (mm2) 170 295 163 91 fmzx (MHz) 38 66 100 200 tox (nm) 20 10 8 6 Metal layers 2 3 4 4 Planarization SOG CMP CMP CMP Poly type n n,p n,p n,p Transistors CMOS SRAM cell area (µm2) Pentium generations BiCMOS BiCMOS BiCMOS Source: Dr. Leon D. Yau, Intel, 10/8/96
Clif Fonstad, 11/5/09 Lecture 16  Slide 21 Moore's Law  Everything* doubles every 2 years. Figure source:
Intel Web Site * Density, speed, performance, transistors per chip, transistors
shipped, transistors per cent, revenues, etc. First stated in
Clif Fonstad, 11/5/09
Lecture 16  Slide 22
1965 as every year; revised to every 2 years in 1975.
Reprinted with permission of Intel Corporation. 6.012  Microelectronic Devices and Circuits Lecture 16  CMOS scaling; The Roadmap  Summary • CMOS gate delay and power
Three key performance metrics: (We want to make them all smaller) Gate Delay = 12 n Lmin2 VDD/ µe(VDD  VT)2
[email protected] ∝ CLVDD2/GD = (Wn/Lmin) µeC*ox VDD (VDD  VT)2/4
PDdyn,max ∝ [email protected]/WnLmin = µeεoxVDD (VDD  VT)2/4 toxLmin2 • CMOS scaling rules
Summary of rules: Constant Efield  scale all dimensions
and all voltages by 1/s
Scaling as: Lmin → Lmin/s
Results in: K → s K
w → w/s
C*ox → s C*ox
tox → tox/s
τ → τ/s
NA → s NA
Pdyn → Pdyn /s2
VT,VBS,VDD → VT/s,VBS/s,VDD/s
PDdyn → PDdyn • The Roadmap; what's next?
Stay tuned: 3D; new semiconductors; performance over size
Clif Fonstad, 11/5/09 Lecture 16  Slide 24 MIT OpenCourseWare
http://ocw.mit.edu 6.012 Microelectronic Devices and Circuits
Fall 2009 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms. ...
View
Full Document
 Fall '09
 CharlesG.Sodini
 Trigraph, Clif Fonstad

Click to edit the document details