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6.012  Microelectronic Devices and Circuits, Fall 2009  10/5/09 posting
CMOS Gate Delays, Power, and Scaling
GATE DELAYS
In the last lecture (Lec. 15) we calculated the gate de
lay for a symmetrical CMOS inverter with
V
Tn
= V
Tp

≡
V
T
, C
o
*
xn
= C
o
*
xp
≡
C
o
*
x
, and K
n
= K
p
,
in which both the n and pchannel devices were mini
mum gate length devices, i.e., L
n
= L
p
= L
min
. The p
channel device was made twice as wide as the nchannel
device to get the desired K equality, because we assumed
µ
e
= 2 µ
h
.
We found that the gate delay was given by:
4 C
L
V
DD
τ
GD
≈
K
n
(V
DD
 V
T
)
2
Replacing C
L
and K
n
, to write this in terms of the device
dimensions, we found after a bit of simple algebra:
12 n
2
V
DD
τ
GD
≈
µ
e
L
m in
(V
DD
 V
T
)
2
POWER
There is zero static power in CMOS so the only con
tribution is the dynamic power
P
ave
= C
L
V
D
2
D
f
where f is the operating frequency and C
L
is the loading
capacitance. This load will be the average fanout, n,
times the input capacitance of a similar CMOS gate, plus
any parasitic interconnect capacitance:
C
L
= n C
o
*
x
(L
min
W
n
+ L
min
W
p
) + C
parasitic
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= 3 n C
o
*
x
L
min
W
n
+ C
parasitic
Neglecting C
parasitic
, we can write
P
ave
= 3 n C
o
*
x
L
min
W
n
V
D
2
D
f
MAXIMUM POWER
The maximum power dissipation will occur when the
gate is operated at its maximum frequency (bit rate),
which is in turn proportional to 1/
τ
GD
. Thus we can say
2
1
P
ave max
∝
3 n C
o
*
x
L
min
W
n
V
D D
τ
GD
1 W
n
=
4 L
min
µ
e
C
o
*
x
V
DD
(V
DD
 V
T
)
2
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 Fall '09
 CharlesG.Sodini
 Integrated Circuit, Vdd, power dissipation, minimum gate length, Pdensity max

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