MIT6_012F09_lec17 - 6.012 Microelectronic Devices and...

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Unformatted text preview: 6.012 - Microelectronic Devices and Circuits Lecture 17 - Linear Amplifier Basics; Biasing - Outline • Announcements Announcements - Stellar postings on linear amplifiers Design Problem - Will be coming out next week, mid-week. • Review - Linear equivalent circuits LECs: the same for npn and pnp; the same for n-MOS and p-MOS; all parameters depend on bias; maintaining a stable bias is critical • Biasing transistors Current source biasing Transistors as current sources Current mirror current sources and sinks • The mid-band concept Dealing with charge stores and coupling capacitors • Linear amplifiers Performance metrics: gains (voltage, current, power) input and output resistances power dissipation bandwidth Multi-stage amplifiers and two-port analysis Clif Fonstad, 11/10/09 Lecture 17 - Slide 1 The large signal models: A p-n diode: qAB IBS qAB: Excess carriers on p-side plus excess carriers on n-side plus junction depletion charge. B qBC BJT: npn (in F.A.R.) C iB’ B B junction depletion charge qBC: C-B junction depletion charge IBS E qBE D MOSFET: iD G S qG: Gate charge; a function of vGS, qDB qG n-channel Clif Fonstad, 11/10/09 !FiB’ qBE: Excess carriers in base plus E- B vDS, and vBS. qDB: D-B junction depletion charge qSB: S-B junction depletion charge qSB Lecture 17 - Slide 2 Reviewing our LECs: Important points made in Lec. 13 We found LECs for BJTs and MOSFETs in both strong inversion and sub-threshold. When vbs = 0, they all look very similar: in iin iout Cm + v in gi - gmv in Ci go out + v out Co common common Most linear circuits are designed to operate at frequencies where the capacitors look like open circuits. We can thus do our designs neglecting them.* BJT ST MOS SI MOS Bias dependences: gi : gm : go : q IC " F kT q IC kT $ IC 0 q ID n kT $ ID 0 2K ID # $ ID ST = sub-threshold SI = strong inversion The LEC elements all depend on the bias levels. Establishing a known, stable bias point is a key part of linear circuit design. We use our large signal models in this design and analysis. ! Clif Fonstad, 11/10/09 * Only when we want to determine the maximum frequency to which our designs can usefully operate must we include the capacitors. Lecture 17 - Slide 3 LECs: Identifying the incremental parameters in the characteristics MOSFET: iD (iD)1/2 Inc. |v BS | gm Q Q go ! Inc. v GS vDS vGS = vDS VT gm = diD/dvGS|Q; gmb = ηgm with η = -dVT/dvBS|Q; go = diD/dvDS|Q BJT: iC ln iB , ln iC iC Q IC IC ! Q iB ! go Inc. i B vCE vCE gm = qIC/kT; gπ = βgm with β = diC/diB|Q; go = diC/dvCE|Q Clif Fonstad, 11/10/09 Lecture 17 - Slide 4 Linear equivalent circuits for transistors (dynamic): Collecting our results for the MOSFET and BJT biased in FAR MOSFET: Cgd g + v gs gmv gs Cgs s- gm = K [VGS " VT (VBS )] [1 + #VDS ] $ d gmb v bs go = go Csb Cdb Cgb K I 2 [VGS " VT (VBS )] # $ # ID = D 2 VA gmb = % gm = % 2 K ID s v bs b+ 2 K ID with % & " 'VT 'v BS = Q 1 * Cox (SiqN A q) p " VBS 2 * Cgs = W L Cox , Csb , Cgb , Cdb : depletion capacitances 3 * * Cgd = W Cgd , where Cgd is the G-D fringing and overlap capacitance per unit gate length (parasitic) ! ! Cµ b g! e q " o IBS e qVBE kT g q IC g% = m = "o " o kT gm = BJT: + v! - C! c gmv ! go e 2 wB C" = gm # b + B-E depletion cap. with # b $ , 2 De Clif Fonstad, 11/10/09 ! go = " o IBS [e qVBE kT kT [1 + #VCE ] $ + 1] # $ # IC = q IC kT IC VA Cµ : B-C depletion cap. Lecture 17 - Slide 5 MOSFETs and BJTs biased for use in linear amplifiers +V +V +V +V IBIAS IBIAS IBIAS -V n-MOS Clif Fonstad, 11/10/09 IBIAS -V p-MOS -V -V npn pnp Lecture 17 - Slide 6 Getting IBIAS: Making a transistor into a current source/sink* ISINK ISINK + + V REF V REF - - + V REF + V REF npn ISOURCE pnp ISOURCE n-MOS p-MOS BJT current sources/sinks MOSFET current sources/sinks Must maintain VCE > 0.2V [VEC in case of pnp] Must maintain VDS > (VREF - VT) [VSD > (VREF + VT) in case of p-MOS] ISOURCE/SINK = [βF/(βF+1)] IES(eqVREF/kT-1) ≈ IESeqVREF/kT ISOURCE/SINK = K(VREF - |VT|)2/2 Clif Fonstad, 11/10/09 * Some people make a distinction between a "sink" and a "source"; you can call them all "sources" if you wish. Lecture 17 - Slide 7 Getting IBIAS: Setting VREF for a current source/sink V+ V+ V+ Circuit being biased Circuit being biased QA + V REF Concept RG1 ISINK ISINK ISINK V- Circuit being biased - QA + RG2 V REF V- MOSFET version - V- Simple resistor divider: too sensitive to device to device variations of VT, K Clif Fonstad, 11/10/09 Lecture 17 - Slide 8 Getting IBIAS: Setting VREF, cont. V+ V+ V+ Circuit being biased Circuit being biased RG1 V REF RG1 ISINK ISINK QA + Circuit being biased + QA ISINK QB QA + V REF - V- MOSFET version Clif Fonstad, 11/10/09 RG2 RS V REF - VDivider with RG: less sensitive to variations in VT, K, but not perfect; resistors are undesirable VCurrent Mirror: matches VT, K variations; easy to bias multiple stages; only 1 R* Lecture 17 - Slide 9 * We'll see how to make this zero.. Current mirror sources/sinks: establishing VREF; setting I V+ V+ MOSFET mirrors + V REF - Q1 RREF Q2 ISINK ISOURCE RREF Q1 V REF - V- V+ V+ BJT mirrors + V REF - Q1 Q2 + ISOURCERREF = (KQ2/KQ1)[V+ - V- - VT - (2ISOURCE/KQ1)1/2] V- RREF ISINKRREF = (AQ2/AQ1)(V+ - V- - 0.6) Q2 ISINK ISOURCE RREF ISINKRREF = (KQ2/KQ1)[V+ - V- - VT - (2ISINK/KQ1)1/2] ISOURCERREF = (AQ2/AQ1)(V+ - V- - 0.6) Q1 Q2 + V REF - V- Clif Fonstad, 11/10/09 NOTE: Base currents have not been accounted for in these expressions V- Lecture 17 - Slide 10 Examples of current mirror biased MOSFET circuits: V+ V+ V+ ID ID ID RREF RREF Q1 IREF Q1 IREF IBIAS -V Q2 Q3 Q2 Q3 Above: Concept Right: Implementations V- V- MOSFET Mirror ID ≈ (KQ3/KQ2) IREF Clif Fonstad, 11/10/09 BJT Mirror ID ≈ (AQ3/AQ2) IREF Lecture 17 - Slide 11 Final comment on current sources: What do they look like incrementally? They look like a resistor with conductance go For example, consider an n-MOS sink: ISINK + V REF - g + v gs = 0 sv bs = 0 b+ d s gmb v bs =0 gmv gs =0 - check it out for yourself - we'll come back to the cascode in Lec. 22 Clif Fonstad, 11/10/09 go s, b, g go V+ ISINK RREF How do you do better (smaller go)? The cascode connection: d Q1 Q2 Q3 Q4 V- Lecture 17 - Slide 12 Linear amplifier layouts: The practical ways of putting inputs to, and taking outputs from, transistors to form linear amplifiers +V There are 12 choices: three possible nodes to connect to the input, and for each one, two nodes from which to take an output, and two choices of what to do with the remaining node (ground it or connect it to something). Not all these choices work well, however. In fact only three do: Name Common source/emitter +V 2 2 1 1 3 3 IBIAS IBIAS -V -V Input Output Grounded 1 2 3 Common gate/base 3 2 1 Common drain/collector (Source/emitter follower) 1 3 2 1 2 none Source/emitter degeneration Clif Fonstad, 11/10/09 Lecture 17 - Slide 13 • Three MOSFET single-transistor amplifiers V+ V+ CO CO + vout - + vin IBIAS CE IBIAS V- + vout CI + vIN - V- COMMON SOURCE Input: gate Output: drain Common: source Substrate: to source COMMON GATE Input: source; Output: drain Common: gate Substrate: to ground vout + vin - - + + vin - V+ Clif Fonstad, 11/10/09 + + vin IBIAS V- SOURCE FOLLOWER Input: gate Output: source Common: drain Substrate: to source + vin + vout vout - CO + vout - - Lecture 17 - Slide 14 Mid-band: the frequency range of constant gain and phase Common emitter example: V+ The linear equivalent circuit for the common emitter amplifier stage on the left is drawn below with all of the elements included: CO + vout - + vin IBIAS Cµ rt + v in g! + CE vt + v! - CO + gmv ! C! gLOAD - V- rIBIAS - go v out gnext CE - The capacitors are of two types: Biasing capacitors: (CO, CE, etc.) Device capacitors: (Cπ, Cµ, etc.) Clif Fonstad, 11/10/09 they are typically very large (in µF range) they will be effective shorts above some ωLO they are typically very small (in pF range) they will be effective open circuits below some ωHI Lecture 17 - Slide 15 Mid-band, cont. At frequencies above some value (≡ ωLO) the biasing capacitors look like shorts: SC CO Cµ rt ωLO < ω + v in g! + v! + - vt + gmv ! C! go gLOAD - rIBIAS v out gnext CE SC - - At frequencies below some value (≡ ωHI) the device capacitors look like open circuits: OC ω < ωHI rt + v in g! + vt + v! OC C! - Cµ CO + gmv ! gLOAD - rIBIAS Clif Fonstad, 11/10/09 go v out gnext CE Lecture 17 - Slide 16 Mid-band, cont. If ωLO < ωHI, then there is a range of frequencies where all of the capacitors are either short circuits (the biasing capacitors) or open circuits (the device capacitors), and we have: OC ωLO < ω < ωHI rt + v in g! + vt SC CO Cµ + v! OC C! - + gmv ! v out gLOAD - rIBIAS go gnext CE SC - - We call the frequency range between ωLO and ωHI, the "mid-band" range. For frequencies in this range our model is simply: + vt - rt + v in g! - + v! - gmv ! go + v out - gl (≡ gLOAD + gnext) Valid for ωLO < ω < ωHI, the "mid-band" range, where all bias capacitors are shorts and all device capacitors are open. Clif Fonstad, 11/10/09 Lecture 17 - Slide 17 Mid-band, cont: The mid-band range of frequencies In this range of frequencies the gain is a constant, and the phase shift between the input and output is also constant (either 0˚ or 180˚). log |A vd | Mid-band Range !LO !b !a !d !c !LO * !HI * !HI !4 log ! ! !5 !2 1 !3 All of the parasitic and intrinsic device capacitances are effectively open circuits All of the biasing and coupling capacitors are effectively short circuits Clif Fonstad, 11/10/09 * We will learn how to estimate ωHI and ωLO in Lectures 23/24. Lecture 17 - Slide 18 Linear amplifier basics: performance metrics The characteristics of linear amplifiers that we use to compare different amplifier designs, and to judge their performance and suitability for a given application are given below: iin + vin - iout Linear Amplifier + vout - Rest of circuit Voltage gain, Av = vout/vin Current gain, Ai = iout/iin Power gain, Apower = Pout/Pin = voutiout /viniin = AvAi Input resistance, rin = vin/iin itest Linear Amplifier + vtest - Output resistance, rout = vtest/itest with vin = 0 DC Power dissipation, PDC = (V+ - V-)(ΣIBIAS's) Clif Fonstad, 11/10/09 Lecture 17 - Slide 19 Linear amplifier basics: multi-stage structure; two-ports iin + vin - iout Linear Amplifier LEC + vout - External Load The typical linear amplifier is comprised of multiple building- block stages, often such as the single transistor stages we introduced on Slide 14 (and which will be the topic of Lect. 19): iin + vin - iout Stage #1 LEC Stage #2 LEC Stage #n-1 LEC Stage #n LEC + External vout Load - A useful concept and tool for analyzing, as well as designing, such multi-stage amplifiers is the two-port representation. Note: More advanced multi-stage amplifiers might include Clif Fonstad, 11/10/09 feedback, the coupling of the outputs of some stages to the Lecture 17 - Slide 20 inputs of preceding stages. This is not shown in this figure. Linear amplifier basics: two-port representations Each building block stage can be represented by a "two-port" model with either a Thévenin or a Norton equivalent at its output: iin iout + vin - Stage #i LEC Clif Fonstad, 11/10/09 Ro or G o iout + v out - A v v in - or R fiin + Thévenin Output iin + v in Gi or R i - + vout - Two-ports can simplify the iin,j analysis and + design of multi-stage v in,j amplifiers: iin + v in Gi or R i - iout Gmv in or A i iin + Go v out or R o - Norton Output Gm,j v in Gi,j Stage j iout,j = iin,j+1 + v out,j = Go,j v in,j+1 - Gi,j+1 iout,j+1 = iin,j+2 + v Go,j+1 out,j+1 = v in,j+2 Gm,j+1 v in,j+1 - Stage j+1 Lecture 17 - Slide 21 Linear amplifier basics: Biasing multi-stage amplifiers V+ + V REF1 - QCS2 QCS4 ICS2 ICS4 + vin - RREF + Stage #1 Stage #3 Stage #2 Stage #5 + - Stage #4 ICS1 QREF vOut ICS3 ICS5 QCS1 QCS3 QCS5 V REF2 - V- ⇒ The current mirror voltage reference method can be extended to bias multiple stages, and one reference chain can be used to provide VREF to all the sources and sinks in an amplifier. Clif Fonstad, 11/10/09 Lecture 17 - Slide 22 Linear amplifier basics: Biasing multi-stage amplifiers. cont. V+ ICS2 ICS4 + vin - + Stage #1 Stage #3 Stage #2 Stage #5 vOut - Stage #4 ICS1 ICS3 ICS5 V- When looking at a complex circuit schematic it is useful to identify the voltage reference chain and the biasing transistors and replace them all by current source symbols. This can reduce the apparent complexity dramatically. Clif Fonstad, 11/10/09 Lecture 17 - Slide 23 6.012 - Microelectronic Devices and Circuits Lecture 17 - Linear Amplifier Basics; Biasing - Summary • Biasing transistors Current source biasing: current sources to establish stable bias pts. large signals models are used in this analysis Transistors as current sources: great as long as stay in FAR Current mirror current sources and sinks: it takes one to know one • Mid-band analysis Biasing capacitors: short circuits above ωLO Device capacitors: open circuits below ωHI Midband: ωLO < ω < ωHI • Linear amplifiers Performance metrics: gains (voltage, current, power) Av = vout/vin, Ai = iout/iin, Apower = voutiout /viniin input and output resistances rin = vin/iin, rout = vtest/itest with vin = 0 dc power dissipation: (V+ - V-)(ΣIBIAS's) bandwidth (We'll save bandwidth for later - Lecs. 23/24) Multi-stage amplifiers: two port models and analysis current mirror biasing of multiple stages Clif Fonstad, 11/10/09 Lecture 17 - Slide 24 MIT OpenCourseWare 6.012 Microelectronic Devices and Circuits Fall 2009 For information about citing these materials or our Terms of Use, visit: ...
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