MIT6_012F09_lec18

MIT6_012F09_lec18 - 6.012 - Microelectronic Devices and...

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Unformatted text preview: 6.012 - Microelectronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline • Announcements Exam Two Results - Exams will be returned tomorrow (Nov 13). • Review - Biasing and amplifier metrics Mid-band analysis: Biasing capacitors: short circuits above ωLO Device capacitors: open circuits below ωHI Midband: ωLO < ω < ωHI Current mirror current source/sink biasing: on source terminal Performance metrics: gains (voltage, current, power); input and output resistances; power dissipation; bandwidth Multi-stage amplifiers: two-port analysis; current source/sink chains • Building-block stages Common source Common gate Source follower Series feedback Shunt feedback Clif Fonstad, 11/12/09 (also called "common drain") (more commonly: "source degeneracy") Lecture 18 - Slide 1 Mid-band: the frequency range of constant gain and phase Cµ V+ Common emitter example: rt + v in g! + CO + vout - + vin - vt + v! - CO + gmv ! C! go gLOAD - rIBIAS gnext CE - - IBIAS v out Biasing capacitors: effective shorts ω > ωLO Device capacitors: effective open circuits ω < ωHI CE V- We call the frequency range between ωLO and ωHI, the "mid-band" range. For frequencies in this range our model is simply: + vt ωLO<ω<ωHI - Clif Fonstad, 11/12/09 rt + v in g! - + v! - gmv ! go + v out - Valid for ωLO < ω < ωHI, the "mid-band" range, where all bias capacitors are shorts and all device capacitors are open. gl (≡ gLOAD + gnext) Lecture 18 - Slide 2 Mid-band, cont: The mid-band range of frequencies In this range of frequencies the gain is a constant, and the phase shift between the input and output is also constant (either 0˚ or 180˚). log |A vd | Mid-band Range !LO !b !a !d !c !LO * !HI * !HI !4 log ! ! !5 !2 1 !3 All of the parasitic and intrinsic device capacitances are effectively open circuits All of the biasing and coupling capacitors are effectively short circuits Clif Fonstad, 11/12/09 * We will learn how to estimate ωHI and ωLO in Lectures 23/24. Lecture 18 - Slide 3 Linear equivalent circuits for transistors (dynamic): Collecting our results for the MOSFET and BJT biased in FAR No velocity saturation; α = 1 MOSFET: Cgd g + v gs gmv gs Cgs s- gm = K [VGS " VT (VBS )] [1 + #VDS ] $ d gmb v bs go = go Csb Cdb Cgb K I 2 [VGS " VT (VBS )] # $ # ID = D 2 VA gmb = % gm = % 2 K ID s v bs b+ 2 K ID with % & " 'VT 'v BS = Q 1 * Cox (SiqN A q) p " VBS 2 * Cgs = W L Cox , Csb , Cgb , Cdb : depletion capacitances 3 * * Cgd = W Cgd , where Cgd is the G-D fringing and overlap capacitance per unit gate length (parasitic) ! ! Cµ b g! e q " o IBS e qVBE kT g q IC g% = m = "o " o kT gm = BJT: + v! - C! c gmv ! go e 2 wB C" = gm # b + B-E depletion cap. with # b $ , 2 De Clif Fonstad, 11/12/09 ! go = " o IBS [e qVBE kT kT [1 + #VCE ] $ + 1] # $ # IC = q IC kT IC VA Cµ : B-C depletion cap. Lecture 18 - Slide 4 Biasing a MOSFET stage with a MOSFET current mirror: The design process: V+ V+ • We have a target ID, and we want to know what size to make RREF to get it. ID ID RREF Q1 IREF IBIAS -V Q2 Q3 Above: Concept Right: Implementation VNote: Q2 is always in saturation. As long as Q3 is also in saturation, its drain current will be (KQ3/KQ2) IREF. Clif Fonstad, 11/12/09 • For simplicity we can make KQ3 = KQ2, so IREF = ID. • Select a KQ2, perhaps that corresponding to a minimum size device. • Calculate what VGS2 (= VREF) is when Q2's drain current is IREF: VREF = VT - (2 IREF/KQ2)1/2 • What RREF must be to make Q2's drain current IREF can then be found from: RREF = [(V+ - V- ) - VREF]/IREF • If RREF has this value, then Q3's drain current will be IREF as long as it is in saturation. Lecture 18 - Slide 5 Linear amplifier basics: Biasing multi-stage amplifiers V+ + V REF1 - QCS2 QCS4 ICS2 ICS4 + vin - RREF + Stage #1 Stage #3 Stage #2 Stage #5 + - Stage #4 ICS1 QREF vOut ICS3 ICS5 QCS1 QCS3 QCS5 V REF2 - V- ⇒ The current mirror voltage reference method can be extended to bias multiple stages, and one reference chain can be used to provide VREF to all the sources and sinks in an amplifier. Clif Fonstad, 11/12/09 Lecture 18 - Slide 6 Linear amplifier basics: Biasing multi-stage amplifiers. cont. V+ ICS2 ICS4 + vin - + Stage #1 Stage #3 Stage #2 Stage #5 vOut - Stage #4 ICS1 ICS3 ICS5 V- When looking at a complex circuit schematic it is useful to identify the voltage reference chain and the biasing transistors and replace them all by current source symbols. This can reduce the apparent complexity dramatically. Clif Fonstad, 11/12/09 Lecture 18 - Slide 7 Linear amplifier basics: performance metrics The characteristics of linear amplifiers that we use to compare different amplifier designs, and to judge their performance and suitability for a given application are given below: iin + vin - iout Linear Amplifier + vout - Rest of circuit Voltage gain, Av = vout/vin Current gain, Ai = iout/iin Power gain, Apower = Pout/Pin = voutiout /viniin = AvAi Input resistance, rin = vin/iin itest Linear Amplifier + vtest - Output resistance, rout = vtest/itest with vin = 0 DC Power dissipation, PDC = (V+ - V-)(ΣIBIAS's) Clif Fonstad, 11/12/09 Lecture 18 - Slide 8 Linear amplifier basics: multi-stage structure; two-ports iin + vin - iout Linear Amplifier LEC + vout - External Load The typical linear amplifier is comprised of multiple building- block stages, often such as the single transistor stages we introduced on Slide 14 (and which will be the topic of Lect. 19): iin + vin - iout Stage #1 LEC Stage #2 LEC Stage #n-1 LEC Stage #n LEC + External vout Load - A useful concept and tool for analyzing, as well as designing, such multi-stage amplifiers is the two-port representation. Note: More advanced multi-stage amplifiers might include Clif Fonstad, 11/12/09 feedback, the coupling of the outputs of some stages to the inputs of preceding stages. This is not shown in this figure. Lecture 18 - Slide 9 Linear amplifier basics: two-port representations Each building block stage can be represented by a "two-port" model with either a Thévenin or a Norton equivalent at its output: iin iout + vin - Stage #i LEC iout + v out - A v v in - or R fiin + iout Gmv in or A i iin + Go v out or R o - Norton Output Gm,j v in Gi,j Stage j Clif Fonstad, 11/12/09 Ro or G o Thévenin Output iin + v in Gi or R i - + vout - Two-ports can simplify the iin,j analysis and + design of multi-stage v in,j amplifiers: iin + v in Gi or R i - iout,j = iin,j+1 + v out,j = Go,j v in,j+1 - Gi,j+1 iout,j+1 = iin,j+2 + v Go,j+1 out,j+1 = v in,j+2 Gm,j+1 v in,j+1 - Stage j+1 Lecture 18 - Slide 10 Linear amplifier layouts: The practical ways of putting inputs to, and taking outputs from, transistors to form linear amplifiers +V There are 12 choices: three possible nodes to connect to the input, and for each one, two nodes from which to take an output, and two choices of what to do with the remaining node (ground it or connect it to something). Not all these choices work well, however. In fact only three do: Name Common source/emitter +V 2 2 1 1 3 3 IBIAS IBIAS -V -V Input Output Grounded 1 2 3 Common gate/base 3 2 1 Common drain/collector (Source/emitter follower) 1 3 2 1 2 none Source/emitter degeneration Clif Fonstad, 11/12/09 Lecture 18 - Slide 11 • Three MOSFET single-transistor amplifiers V+ V+ + + + vin v in - CO CO + + vout vout -IIBIAS BIAS CE + IBIAS IBIAS vout out CII + + vIIN vN - VV- V -COMMON SOURCE Input: gate Output: drain Common: source Substrate: to source COMMON GATE Input: source; Output: drain Common: gate Substrate: to ground vout + vin - - + + vin - V+ Clif Fonstad, 11/12/09 + + vin IBIAS V- SOURCE FOLLOWER Input: gate Output: source Common: drain Substrate: to source + vin + vout vout - CO + vout - - Lecture 18 - Slide 12 • Single-transistor amplifiers with feedback V+ CO + vout - + vin - RF IBIAS RF + vin - CE CE V- PARALLEL FEEDBACK* SERIES FEEDBACK RF + vin Clif Fonstad, 11/12/09 CO + vout - IBIAS V- + V+ + vout RF - + vin - * Also termed "source degeneracy" vout Lecture 18 - Slide 13 V+ • Common source amplifier Common source • Input to gate • Output from drain • Source common to input and output, and grounded CO + vout + vin - External Load IBIAS CE rt + vt - Vg d + v in = v gs gmv gs go gsl s,b + v out - gel s,b Mid-band LEC for common source Clif Fonstad, 11/12/09 Lecture 18 - Slide 14 Common source amplifier, cont. rt g d + v in = v gs + vt - gmv gs go gsl - + v out - gel s,b s,b v out = " gm v in gm v t =" go + gsl + gel go + gsl + gel a large |#| Two-ports: iout iin + v in Gi - ! Gmv in Gi = 0 (Ri = ") Go = ( go + gsl ) ! Clif Fonstad, 11/12/09 ! Go + v out - Ro iin + v in Gi - Gm = "gm + - A v v in gm Av = " go + gsl A good workhorse gain stage ! ! iout + v out - # Gm & %= ( $ Go ' Lecture 18 - Slide 15 • Source follower (common drain) amplifier V+ Source Follower (Common drain) • Input to gate • Output from source • Drain common to input and output, and incrementally grounded + vin - CO + vout IBIAS - VMid-band LEC for source follower (common drain) g rt + vt - d,b ++ v in v gs - gmv gs s gcs Clif Fonstad, 11/12/09 External Load gel go gmb v bs + v bs - s + v out =-v ds =-v bs Lecture 18 - Slide 16 Source follower (common drain) amplifier, cont. v gs = v in -v out + + -s s g + vt rt v in - - gmv gs gcs gmb d,b v out = gm (v in " v out ) gmb + go + gcs + gel Two-ports: ! iin + v in Gi - gel go d,b # v out = gm v in gv v $ m in = in gm + gmb + go + gcs + gel gm + gmb 1 + % ≈1 Ro + - A v v in 1 Av " 1+ # Gi = 0 iout + v out - (Ri = ") iin + v in Gi - iout Gmv in Go + v out - Gm = Av Go = gm Go = ( gm + gmb + go + gcs ) " ( gm + gmb ) = (1 + #) gm ! ! A great output buffer stage with small Rout and large Rin; Av ≈ 1, Ai large. !Clif Fonstad, 11/12/09 ! + v out - Lecture 18 - Slide 17 V+ • Common gate amplifier Common Gate • Input to source • Output from drain • Gate common to input and output, and grounded CO IBIAS Mid-band LEC for common gate CI + vIN - + vout External Load - V- g d + gmv gs rt s+ + vt - v in = -v bs = -v gs - go gmb v bs v out s gel gsl - b Clif Fonstad, 11/12/09 Lecture 18 - Slide 18 Common gate amplifier, cont. go rt iin s+ + vt - v in = v sg - d (gm + gmb )v sg g,b gsl " v out = (gm + gmb + go )v in ( gsl + gel + go ) Current gain - Current divider gsl/gel noting that iin = - id: iin i gel v out = = out " iout = i (gsl + gel ) gel ( gsl + gel ) in ! + v out - gel g,b Voltage gain - KCL at drain node: (gm + gmb )v in = (gsl + gel )v out + go (v out + v in ) iout # (1 + $)gm ( gsl + gel + go ) a large |#| ≈ 1 if gsl small Input resistance - Use vout(iin) and vout(vin) expressions:) i ( g + gmb + go )v in " v out = ! in , v out = m (gsl + gel ) ( gsl + gel + go ) v 1 1 (gsl + gel + go ) Rin = in = " = iin ( gsl + gel )( gm + gmb + go ) ( gm + gmb ) (1 + #) gm ! Clif Fonstad, 11/12/09 v in small Lecture 18 - Slide 19 Common gate amplifier, cont. go rt d s itest* + (gm + gmb )v sg + v sg v test* g,b itest gsl + v test - g,b Output resistance - Set vt = 0, and apply vtest* to output; find itest*: i go itest * = go (v test * " itest * rt ) " ( gm + gmb )itest * rt # Go = gsl + test * = gsl + v test * 1 + rt ( gm + gmb + go ) a small # Two-port: ! Ri " 1 (1 + #) gm (Ri very small) Ai = gel ( gel + gsl ) " 1 ! ! go Go " gsl + 1 + rt ( gm + gmb ) Clif Fonstad, 11/12/09 ! ( Ro very large) iin + v in Ri iout A iiin - A very small Ri, very large Ro stage often used to complement other stages; Ai ≈ 1, Av large. Ro + v out - Lecture 18 - Slide 20 V+ • Series Feedback: source degeneracy Series feedback • Output signal fed back to the input through a passive element that is common to the input and output circuits. + vin - Useful in discrete device circuit design; we use it to understand common-mode gain suppression in differential amplifiers Mid-band LEC: rt + v in + g + gmv gs - s,b go s,b gsl v out We find: gel Av = v out v in " # rl RF rl $ 1 ( gsl + gel ) RF - CE V- - vt RF IBIAS d + v gs CO + vout - - Clif Fonstad, 11/12/09 Lecture 18 - Slide 21 ! V+ • Feedback: shunt feedback element Shunt feedback • Output signal fed back to the input through a passive element forming a bridge between the input and output. Used to stabilize high gain circuits and in transimpedance amplifiers; the same topology leads to the Miller effect. (Lec 23) Mid-band LEC: rt + vt - g + v in = v gs RF + vin IBIAS CE RF d gmv gs CO + vout - V- go gsl s,b + v out - gel s,b We find: Av = v out v in " #gm RF Clif Fonstad, 11/12/09 Lecture 18 - Slide 22 • Summary of the single transistor stages (MOSFET) Voltage gain, Av MOSFET Common source " gm (= "gm rl' ) [go + gl ] * [ gm + gmb ] rl' Common gate [gm ] *1 gm + gmb + go + gl ] [ Source degeneracy r *" l (series feedback) RF [ g " GF ] * " g R Shunt feedback "m mF [ go + G F ] Source follower Current gain, Ai Input resistance, Ri # # *1 * 1 [gm + gmb ] Output resistance, Ro $ 1' ro & = ) % go ( + [ gm + gmb + go ] . * ro ,1 + / gt 0 1 1 * [ gm + go + gl ] gm # # # # * ro g "l GF 1 GF [1 " Av ] $ ' 1 ro || RF & = ) [go + GF ] ( % Power gain, A p = Av " Ai Clif Fonstad, 11/12/09 Note: When vbs = 0 the gmb factors should be deleted. ! Lecture 18 - Slide 23 6.012 - Microelectronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Summary • Amplifier Building-blocks - single transistor stages Common source: good voltage and current gain large Rin and Rout good gain stage Common gate: very small Rin; very large Rout unity current gain; good voltage gain will find paired with other stages to form "cascode" Source follower: very small Rout; very large Rin unity voltage gain; good current gain an excellent output stage or buffer Series feedback: moderate voltage gain dependant on resistor ratio Shunt feedback: used in transimpedance amplifiers Clif Fonstad, 11/12/09 Lecture 18 - Slide 24 MIT OpenCourseWare http://ocw.mit.edu 6.012 Microelectronic Devices and Circuits Fall 2009 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms. ...
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