MIT6_012F09_lec20

MIT6_012F09_lec20 - 6.012 - Microelectronic Devices and...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 6.012 - Microelectronic Devices and Circuits Lecture 20 - Diff-Amp Anal. I: Metrics, Max. Gain - Outline • Announcements Announcements - D.P.: No Early effect in large signal analysis; just LECs. Lec. 21 foils useful; Sp 06 DP foils, too (on Stellar) Do PS #10: free points while working on D.P. • Review - Differential Amplifier Basics Difference- and common-mode signals: vID = vIN1- vIN 2, vIC = (vIN1+ vIN2)/2 Half-circuits: half of original with wires shorted or cut (familiar, easy analyses) • Performance metrics - specific to diff. amps. Difference- and common-mode gains Common-mode rejection ratio Input and output voltage swings • Non-linear loads The limitation of resistive loads: Gain limited by voltage supply Non-linear loads: High incremental resistance/small voltage drop • Active loads Lee load Current mirror load Clif Fonstad, 11/19/09 Lecture 20 - Slide 1 Differential Amplifiers - overview of features and properties Intrinsic advantages and features: - large difference mode gain - small common mode gain - easy to cascade stages; no coupling capacitors - no emitter/source capacitors in CS/CE stages Performance metrics: - difference mode voltage gain, Avd - common mode voltage gain, Avc - input resistance, Rin - output resistance, Rout - common mode input voltage range - output voltage swing - DC offset on output - Power dissipation Clif Fonstad, 11/19/09 Today Today ∞ Lec 21 Today Today Lec 21 Lec 18 Lecture 20 - Slide 2 Differential Amplifiers - common-mode input range (VC,min ≤ vC ≤ VC,max) vGS stays constant We have said the output changes very little for common-mode inputs. This is true as long as the vC doesn't push the transistors out of saturation. There are a minimum and maxiumum vC: VC, max: As vC increases, vDS8 and vDS9 decrease until Q8 and Q9 are no longer in saturation. Q4 + Q5 vC up vC down v DS gets smaller + Q8 vDS + vGS + vDS - + - - + vGS stays constant B Q8, Q9 forced out of saturation if v C too high vC Q9 up - - VC, min: As vC decreases, vDS10 decreases until Q10 is no longer in saturation. Clif Fonstad, 11/19/09 + 1.5 V +Q 7 Q6 - v DS gets smaller vDS Q10 + - - vGS vc down Q10 forced out of saturation if v c too low - 1.5 V The node between Q8/Q9 and Q10 moves up and down with vC. Lecture 20 - Slide 3 Differential Amplifiers - output voltage range + 1.5 V Fixed + ++ v v SG16 SG12 Q12 v SD12 - + Q13 ! 0.6V -+ v DS15 + v GS15 - Q15 - AQ16 (VOUT,min ≤ vOUT ≤ VOUT,max) + v SD12 and v SD16 decrease as vOUT goes up, so Q 12 and/or Q 16 may be forced out of v SD16 saturation if v OUT is too high - + Q20 vOUT + ! 0.6V up ! 0.6V -Q + Q18 ! 0.6V + vOUT 17 ! 0.6V - Q down 21 Q19 + v DS19 B+ v DS15 and v DS19 decrease Fixed v GS19 -- 1.5 V as v OUT goes down, so Q15 and/or Q 19 may be forced out of saturation if vOUT is too low As vOUT goes down, Q15 and/or Q19 may go out of saturation; as vOUT goes up, the same may happen to Q12 and/or Q16. Clif Fonstad, 11/19/09 Lecture 20 - Slide 4 Differential Amplifier Analysis incremental analysis exploiting symmetry and superposition + vid - a LEHC: one half of sym. LEC + vod - + vic - No voltage on common links, so incrementally they are grounded. a LEHC: one half of sym. LEC + voc Clif Fonstad, 11/19/09 a LEHC: one half of sym. LEC + vid - + -vod - a LEHC: one half of sym. LEC No current in common links, so incrementally they are open. + -vid - + voc - a LEHC: one half of sym. LEC + vod = A vdvid - + vic - + vic - a LEHC: one half of sym. LEC + voc = A vc vic Lecture 20 - Slide 5 Looking at the design problem circuit: Lesson - Draw the difference and common mode half circuits. roLL dm Difference mode half circuit: roCM dm Q17 + vid - Q8 + roQ 16 roLL cm Common mode half circuit: Q12 vic - Q8 2roQ 10 vod - RLOAD roCM cm Q17 + Q20 Q20 + Q12 roQ 16 voc RLOAD - We have reduced the transistor count from 22 to 4, and we see that our complex amplifier is a just cascade of 4 single-transistor stages. Clif Fonstad, 11/19/09 Lecture 20 - Slide 6 V+ What's with these active, nonlinear loads? Why doesn't the design problem use resistors? RSL Linear Resistor Loads: the limit on maximum stage gain - with linear resistor loads we must make a compromise between the voltage gain and the size of the output voltage swing. Maximum voltage gains g CO gmv gs - go + v out - vout - + vin IBIAS d + v in = v gs + Q CS G SL (=1/RSL ) V- MOSFET : Av ,max = gm RSL = 2 [ ID RSL ] max 2 ID RSL $ [VGS # VT ] [VGS # VT ] min Bipolar : Av,max = gm RSL = [I R ] qIC RSL $ C SL max kT VThermal s,b s,b " What are [ICRSL]max, [IDRSL]max, and [VGS - VT]min ? ! Clif Fonstad, 11/19/09 * For a MOSFET, gm = (2KID/α)1/2 = K(VGS - VT)/α = 2ID/(VGS - VT) Lecture 20 - Slide 7 Resistor Loads: cont. - What are [IDRSL]max, [ICRSL]max, and [VGS - VT]min? [IDRSL]max, [ICRSL]max: - [IDRSL]max and [ICRSL]max are determined by the desired voltage swing at the output and/or by the commonmode input voltage range. - The ultimate limit is the power supply. [VGS - VT]min: - [VGS - VT]min is set by how close to threshold the gate can safely be biased before the strong inversion, drift model fails. We will say more about this shortly (Slide 23). Clif Fonstad, 11/19/09 V+ RSL CO Q + vin - + vout - IBIAS CS V- Lecture 20 - Slide 8 Current Source Loads: Incrementally large resistance Relatively small quiescent voltage drop - - transistors with a DC input voltage, i.e. set up as sources/sinks - MOSFET: g + v gs = 0 sv bs = 0 +b + V REF + V REF - d gmv gs =0 go = " I D = Bipolar: + V REF - b + V REF gmv ! =0 e - Clif Fonstad, 11/19/09 + v != g! ! 0 - s go s, b, g c gmb v bs =0 d c e go e, b go ID VA go IC go = " IC = VA Lecture 20 - Slide 9 V+ Current Source Loads: the limit on the maximum stage gain IStage Load CO - current source loads eliminate the need to compromise between the voltage gain and the output voltage swing d + v in = v gs gmv gs + v out - go - IBIAS V[VGS # VT ] Av ,max MOSFET : Bipolar : !lif Fonstad, 11/19/09 C 2 VA ,eff 2 ID gm = = $ go + gsl ID VA ,Q + ID VA ,SL [VGS # VT ] min Av,max " with VA ,eff " CS gsl s,b s,b vout - + vin - Maximum voltage gains g + Q VA ,eff gm qIC kT = = = go + gsl IC VA ,Q + IC VA ,SL Vt VA ,QVA ,SL [V A ,Q + VA , SL ] , Vt " kT q Typically VA,eff >> [ID RSL]max * For a MOSFET, gm = (2KID/α)1/2 = K(VGS - VT)/α = 2ID/(VGS - VT) Lecture 20 - Slide 10 Current Source Loads: the maximum stage gain, cont. - the similarity in the results for BJT's and MOSFETs operating in strong inversion extends to MOSFETs operating sub-threshold and in velocity saturation, also: g d + v in = v gs gmv gs go - + v out - gsl s,b s,b The MOSFET LEC: the same for all. Maximum voltage gains MOSFET sub - threshold : iD = IS ,s" t e( vGS "VT ) nVt , gm = VA ,eff gm ID nVt = = = go + gsl ID VA ,Q + ID VA ,SL nVt Av,max MOSFET w. velocity saturation : ID (vGS " VT ) VA ,QVA ,SL [V A ,Q Clif Fonstad, 11/19/09 * * iD = W ssat Cox (vGS " VT ), gm = W ssat Cox = VA ,eff ID (vGS " VT ) gm = = # go + gsl ID VA ,Q + ID VA ,SL (vGS " VT ) min Av,max with VA ,eff " ID nVt + VA ,SL ] Lecture 20 - Slide 11 Current Source Loads: Example - biasing a source-coupled pair differential amplifer stage Want: Build: V+ V+ Q1 ILOAD Q4 + vIN1 - + vO1 - Q3 Q2 ILOAD + vO2 - Q5 + vIN2 - R1 Q4 + vIN1 - + vO1 - + vO2 - Q5 + - IBIAS Q7 VNote: I LOAD = I BIAS /2 Q6 V- Note: W1 = W2 = W3 W7 = 2W6 This is nice…can we do even better? Yes, with active loads. Consider… Clif Fonstad, 11/19/09 Lecture 20 - Slide 12 Active Loads: Loads that don't just sit there and look pretty. First example: the current mirror load V+ Q1 Q2 Signal actively fed from left side to right side, and applied inputs to "stage load" MOSFETs. + Q3 + vI1 VClif Fonstad, 11/19/09 I BIAS , rob Q4 + vI2 - vOUT - Now "single ended," i.e. only one output, but it is twice as large: vout = 2vout1 Load self-adjusting; circuit forces ILOAD = IBIAS/2. Lecture 20 - Slide 13 Active Loads: The current mirror load, cont. V+ Large differential-mode gain, small common-mode gain. Also provides high gain conversion from doubleended to single-ended output. The circuit is no longer symmetrical, so half-circuit techniques can not be applied. The full analysis is found in the course text. We find: Q1 Q2 id id 2id id id + vid/2 - Q4 Q3 V- Difference-mode inputs Clif Fonstad, 11/19/09 v out ,d I BIAS , rob + + -vid/2 - vOUT - 2 gm 3 = v id 2 ( go2 + go 4 + gel ) Lecture 20 - Slide 14 ! Active Loads: The current mirror load V+ Q1 Common-mode inputs v out ,c = gob v ic 2 gm 2 Q2 ic ic 0 ic ic + vic - ! With both inputs: v out Q4 Q3 V- I BIAS , rob + vic - + vOUT - 2 gm 3 (v in1 " v in 2 ) " gob (v in1 + v in 2 ) = 2 2 gm 2 2 (go 2 + go4 + gel ) Note: In D.P. the output goes to the base of two BJTs; gel ≠ 0 and can be important. Clif Fonstad, 11/19/09 Lecture 20 - Slide 15 ! What if we want an active load and yet stay differential? Active Loads - The Lee load A load for a fullydifferential stage that looks like a large resistance in difference-mode and small resistance in commonmode) The conventional schematic is drawn here, but the coupling of the load and what is happening is made clearer by redrawing the circuit (next slide.) Clif Fonstad, 11/19/09 Q1 Q5 + vI1 - V+ Q2 Q3 + + vO1 vO2 - V- I BIAS , rob Q4 Q6 + vI2 - Normal format Lecture 20 - Slide 16 Active Loads - The Lee load. cont. Drawn as on the right we see that the load MOSFETs on each side are driven by both outputs. The result is different if the two outputs are equal and opposite (diffmode operation) or if they are equal (common-mode). The next few slides give the results for each mode. Q1 Q3 + vO1 - Q5 + vI1 - V+ Q2 + vO2 + - vO1 - + vO1 - V- Q4 + vO2 - + vO2 - Q6 + vI2 - I BIAS , rob Drawn to highlight cross-coupling and demonstrate symmetry Clif Fonstad, 11/19/09 Lecture 20 - Slide 17 V+ Q1 The Lee load: analysis for difference-mode inputs Q3 + vod + - - -vod vod + vod - Q5 + vid - + - Q4 + -vod - + -vod - V- LEHC: difference-mode + v id /2 = v gs5 - Q2 Q6 + -vid - I BIAS , rob + gm5v id /2 go5 go1 gm1v od /2 -gm3v od /2 go3 v od /2 - gel goLLd Clif Fonstad, 11/19/09 Lecture 20 - Slide 18 The Lee load: analysis for difference-mode inputs, cont LEHC: difference-mode + v id /2 = v gs5 - + gm5v id /2 + v id /2 = v gs5 - go5 -gm3v od /2 gm1v od /2 go3 v od /2 - gel + gm5v id /2 g go5 gm1 go1 -gm1 go1 v od /2 - gel d + v id /2 = v gs5 s,b go1 + gm5v gs5 go5 goLLd v od /2 - gel goLLd = 2 go1 s,b v od " gm 5 Avd = = v id ( go 5 + 2 go1 + ge! 1) Clif Fonstad, 11/19/09 Note: In D.P., the outputs go to MOSFET gates so gel = 0. Lecture 20 - Slide 19 V+ Q1 Q3 Q2 Q4 The Lee load: + analysis for common-mode inputs - + voc - Q5 + voc - v ic - Q6 + vI2 - I BIAS , rob + v gs5 - voc + voc - V- LEHC: common-mode + + + voc + - voc - voc + gm5v gs5 go5 go1 gm1v oc gm3v oc go3 v oc gel gob /2 Clif Fonstad, 11/19/09 - goLLc Lecture 20 - Slide 20 The Lee load: analysis for common-mode inputs, cont LEHC: common-mode + + + v gs5 gm5v gs5 - v ic go5 gm1 go1 gm1 go1 v oc gel gob /2 - g + v ic d + v gs5 - + gm5v gs5 s,b s,b goLLc = 2 ( gm1 + go1 ) go5 goLLc v oc gel " 2 gm1 gob /2 - - ! v oc " gob gob Avc = = #" v ic 2[2( gm1 + go1 ) + ge1 ] 4 gm1 Clif Fonstad, 11/19/09 Note: In D.P., the outputs go to MOSFET gates so gel = 0. Lecture 20 - Slide 21 Achieving the maximum gain: Comparing linear resistors, current sources, and active loads Maximum Gains MOSFET (SI) Bipolar-like (BJT and Sub-VT MOS) Linear resistor loads " Current source loads " Active loads Difference mode $ Common mode $ 2 [ ID RSL ] max [vGS # VT ] min 2 VA ,eff [vGS # VT ] min 2 VA ,eff [vGS # VT ] min [vGS # VT ] min 2 VA ,bias " [IC RSL ] max " $ n Vt VA ,eff n Vt VA ,eff n Vt n Vt $ VA ,bias Observations: - Non-linear (current source) loads typically yield much higher gain than linear resistors, i.e. VA,eff >> [IDRSL]max. - The bias point is not ! important to BJT-type stage gain. as - An SI MOSFET should be biased just above threshold for highest gain. - For active loads what increases Avd, decreases Avc. Clif Fonstad, 11/19/09 Lecture 20 - Slide 22 Achieving the maximum gain: (vGS-VT)min = ? For SI-MOSFETs, maximizing the voltage gain (Av or Avd) requires minimizing (VGS-VT). What is the limit? Sub - threshold : Av 1 = VA n Vt Strong inversion : Av 2 = VA (VGS " VT ) Av/VA is a smooth curve, so clearly (VGS-VT)min > 2nVt. ? Note: n = 1.25 was assumed. Clif Fonstad, 11/19/09 Lecture 20 - Slide 23 6.012 - Microelectronic Devices and Circuits Lecture 20 - Diff-Amp Analysis I - Summary • Performance metrics - specific to diff. amps. Difference- and common-mode gains: Avd = vod/vid, Avc = voc/vic Common-mode rejection ratio: CMRR = Avd/Avc Common-mode input range • Non-linear loads Transistors biased in their constant current regions: MOSFETs in saturation BJTs in their FAR • Active loads Current mirror load: Achieves double- to single-ended conversion without loss of gain Has high resistance for difference-mode signals Has low resistance for common-mode signals Lee Load: Maintains differential signals Has high resistance for difference-mode signals Has low resistance for common-mode signals Clif Fonstad, 11/19/09 Lecture 20 - Slide 24 MIT OpenCourseWare http://ocw.mit.edu 6.012 Microelectronic Devices and Circuits Fall 2009 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms. ...
View Full Document

This note was uploaded on 11/07/2011 for the course COMPUTERSC 6.012 taught by Professor Charlesg.sodini during the Fall '09 term at MIT.

Ask a homework question - tutors are online