MIT6_012F09_lec21

MIT6_012F09_lec21 - 6.012 - Microelectronic Devices and...

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Unformatted text preview: 6.012 - Microelectronic Devices and Circuits Lecture 21 - Diff-Amp Anal. II: Output Stages - Outline • Announcements DP: Get help before the Thanksgiving break. It's due Friday, Dec. 4 On Stellar: Write-up on the cascode connection posted under Lec. 21 Lee Load and Current Mirror Load write-ups posted under Lec. 20. • Review - Non-linear and Active Loads Maximum gain: Av,max ∝ VA,eff/ (VGS- VT)min for MOS; ∝ VA,eff/ Vthemal for BJT Lee Load, Current Mirror: foils on analysis of CM in DP • Specialty Stages - useful transistor pairings Source-coupled pairs The Marvelous Cascode: Postponed until Lecture 22 Push-pull or Totem Pole output stages • Performance metrics - continuing down the list Output resistance: Driving a load DC off-set on output: High impedance nodes; feedback connections Power dissipation: Add up currents from voltage supplies Clif Fonstad, 11/24/09 Lecture 21 - Slide 1 Achieving the maximum gain: Comparing linear resistors, current sources, and active loads Maximum Gains MOSFET (SI) Bipolar-like (w. and w.o. velocity sat.) (Sub-VT MOS and BJT) Linear resistor loads " Current source loads " Active loads Difference mode $ Common mode $ 2 [ ID RSL ] max [vGS # VT ] min 2 VA ,eff [vGS # VT ] min 2 VA ,eff [vGS # VT ] min [vGS # VT ] min 2 VA ,bias [IC RSL ] max " n Vt " $ VA ,eff n Vt VA ,eff n Vt n Vt $ VA ,bias Observations/Comments: - Non-linear (current source) loads typically yield much higher gain than - linear resistors, i.e. VA,eff >> [IDRSL]max. The bias point is not! important to BJT-type stage gain. as An SI MOSFET should be biased just above threshold for highest gain. For active loads what increases Avd, decreases Avc. Making L larger increases VA proportionately, but at the cost of speed. Clif Fonstad, 11/24/09 Lecture 21 - Slide 2 Achieving the maximum gain: (vGS-VT)min = ? For SI-MOSFETs, maximizing the voltage gain (Av or Avd) requires minimizing (VGS-VT). What is the limit? Sub - threshold : Av 1 = VA n Vt Strong inversion : Av 2 = VA (VGS " VT ) Av/VA is a smooth curve, so clearly (VGS-VT)min > 2nVt. ? Note: n = 1.25 was assumed. Clif Fonstad, 11/24/09 Lecture 21 - Slide 3 Active Loads: The current mirror load V+ Large differential-mode gain, small common-mode gain. Also provides high gain conversion from doubleended to single-ended output. The circuit is no longer symmetrical, so half-circuit techniques can not be applied. The full analysis is found in the course text. We find: Q1 id id 2id id id + vid/2 - Difference-mode inputs Clif Fonstad, 11/24/09 Q2 Q4 Q3 Vv out ,d = I BIAS , rob + -vid/2 - + vOUT - 2 gm 3 v id 2 ( go2 + go 4 + gel ) Lecture 21 - Slide 4 Active Loads: The current mirror load, cont. V+ Q1 Common-mode inputs v out ,c = gob v ic 2 gm 2 ic With both inputs: v out ic 0 ic ic + vic - ! Q2 Q4 Q3 V- I BIAS , rob + + vic - vOUT - 2 gm 3 (v in1 " v in 2 ) " gob (v in1 + v in 2 ) = 2 2 gm 2 2 (go 2 + go4 + gel ) Note: In D.P. the output goes to the gate of a BJT; gel matters. Clif Fonstad, 11/24/09 ! Lecture 21 - Slide 5 Active Loads: A current mirror load variant (D.P. version) V+ In the design problem we have a current mirror stage that is not biased by a current source, but rather by the preceding stage*. It thus looks like that on the right. We can do an LEC analysis of this circuit fairly easily. We start with the LEC for the left side and find vinner: Q3 + vIC + vID /2 - + v ic +v id /2 = v gs3 - Q1 Q2 + + Q4 + vIC - vID /2 - vINNER - vOUT - V+ gm3v gs3 go3 gm1 go1 v inner - LEC for the left side * Notice that it is possible to make the bias currents in the two legs of the mirror (Q1/Q3 and Q2/Q4) different by making the transistors widths different. Clif Fonstad, 11/24/09 Lecture 21 - Slide 6 Active Loads: A current mirror load variant, cont. The left side LEC gives: v inner # " gm 3 v id & = % v ic + ( 2' (go 3 + go1 + gm1) $ Note: Make gm1 = gm3, gm2 = gm4, go1 = go3, and go2 = go4. Next we analyze the right side LEC: + !ic -v id /2 = v gs4 v - gm4v gs4 This then gives us vout: v out go4 gm2v inner go2 + v out - gel LEC for the right side # # " gm 4 v id & " gm 2 " gm 3 v id & = % v ic " ( + %v + ( $ ' ( go 4 + go 2 + gel ) ( go 3 + go1 + gm1 ) $ ic 2 ' 2 (go 4 + go2 + gel ) , ) , gm 4 v id ) gm 3 gm 4 gm 3 = v ic +1 " +1 + ." . go 4 + go 2 + gel ) 2 * ( go 3 + go1 + gm1 ) - ( go 4 + go 2 + gel ) * ( go 3 + go1 + gm1) ( / 2 gm 4 2 go1 (v in1 + v in 2 ) (v in1 " v in 2 ) " gm 4 2 2 (2 go4 + gel ) (2go 4 + gel ) gm1 Avd Clif Fonstad, 11/24/09 Avc≈ 1 Note: The difference-mode response is unchanged, but now Avc ≈ 1, not << 1. Lecture 21 - Slide 7 An aside: More on the design problem CM stage Transistor Q13 does not have a companion on the left side of the second DP gain stage (the Current Mirror). If we ignore the Early effect for the large signal biasing analysis, as you have been told to do, this is fine. However, strictly speaking, it is best to maintain symmetry and thus you should add a companion transistor, Q13', as shown to the right. + 1.5 V Q12 Q11 A Q16 Q13' Q13 Q14 Q17 Q15 - 1.5 V Clif Fonstad, 11/24/09 Lecture 21 - Slide 8 Specialty Pairings: The Source-coupled Pair Two coupled common-source stages Large differential gain Common-mode rejection Easy to cascade Easy to bias + vi1 - V+ + vo1 vo2 vi2 IBIAS VDiscussed in Lecture 19. Clif Fonstad, 11/24/09 Lecture 21 - Slide 9 Specialty Pairings: The Cascode (postponed until Lec. 22) Common-source stage followed by a common gate stage V+ Common-source voltage gain Very large output resistance Improved high frequency performance Common Gate CO + V GG External Load vout - Common Source + vin IBIAS CE V- Clif Fonstad, 11/24/09 Lecture 21 - Slide 10 Specialty Pairings: The Push-pull or Totem Pole Output A stacked pair of complementary emitter- or source-followers Large input resistance Small output resistance Voltage gain near one Low quiescent power V+ npn or n-MOS follower pnp or p-MOS follower Qn + vin+V BEn + vin-V EBp - + vout Qp - VClif Fonstad, 11/24/09 V+ + vin+V GSn RL + vin-V SGp - Qn + vout Qp - RL VLecture 21 - Slide 11 Specialty pairings: Push-pull or Totem Pole Output Pairs The limitations of using a simple follower stage* output: - Using a single source follower as the output stage must be biased with a relatively large drain current to achieve a large output voltage swing, which in turn dissipates a lot of quiescent power. + 1.5 V Load current is supplied through Q28 as it turns on more strongly vIN goes positive + vIN - + 1.5 V Q28 v goes positive OUT + IBIAS - 1.5 V Clif Fonstad, 11/24/09 + vIN - Q Q + RL As Q turns off I BIAS flows through load. Turns off Negative v OUT swing limited to -I BIAS RL vOUT RL - The Problem vOUT - vIN goes negative IBIAS - 1.5 V * source follower or emitter follower Lecture 21 - Slide 12 Specialty pairings: Push-pull or Totem Pole, cont. - A p-MOS follower solves the As Q turns off I BIAS flows through load. The Problem negative swing problem, but has its own positive swing problem. + 1.5 V IBIAS Positive v OUT swing limited to I BIAS RL - 1.5 V Clif Fonstad, 11/24/09 V+ + vIN - Q2 supplies the load current for vOUT > 0 Q1 Q2 Q3 + vIN goes positive + vIN - - The solution is to combine the two in a totem pole stack (and drive and bias them by the preceding stage). Q vOUT Turns off RL Q4 - Q3 and Q4 bias Q2 and Q5. They also insure that Q5 turns off as Q2 turns on, and visa versa. Q5 IBIAS V- + vOUT - Q5 sinks the load current for vOUT < 0 Lecture 21 - Slide 13 Specialty pairings: Push-pull or Totem Pole, cont. Comments/Observations: - The output resistance is largest around vOUT = 0. Here both Q2 and Q5 are active and the output resistance is: 1 rout " V+ g +g m2 + vIN - Q1 Q2 - One must always make K2/K3 = K5/K4, and in the typical design K3 = K4, and K2 = K5. The bias current of Q2 and Q5 is set by IBIAS: ! ID 2 = ID 5 = (K 2 K 3 ) IBIAS Q3 Q4 Q5 m5 + vOUT ! IBIAS V- |vOUT| vs |vIN| is fairly linear over a wide range (see right); |vGS| increases slowly with |vIN|. Clif Fonstad, 11/24/09 Lecture 21 - Slide 14 Specialty pairings: Push-pull or Totem Pole, cont. Voltage gain: - The design problem uses a bipolar totem pole. The gain and linearity of this stage depend on the bias level of the totem pole. The gain is higher for with higher bias, but the power dissipation is also. + 1.5 V To calculate the large signal transfer characteristic of the bipolar totem pole we begin with vOUT: vOUT = RL ("iE 20 " iE 21 ) The emitter currents depend on (vIN - vOUT): + vin+V BE20 + iE 20 = "IE 20e( v IN " vOUT ) Vt , iE 21 = IE 21e"( v IN " vOUT ) Vt ! Q20 + vout Q21 - 50! ! Clif Fonstad, 11/24/09 ( v out = RL IE 20 e( v in " v out ) Vt " e"( v in " v out ) Vt = 2 RL IE 20 sinh (v in " v out ) Vt vin-V EB21 - 1.5 V Putting this all together, and using IE21 = - IE20, we have: ! ) We can do a spread-sheet solution by picking a set of values for (vIN - vOUT), using the last equation to calculate the vOUT, using this vOUT to calculate vIN, and finally plotting vOUT vs vIN. The results are seen on the next slide. Lecture 21 - Slide 15 Voltage gain, cont.: - With a 50 Ω load and for several different bias levels we find: The gain and linearity are improved by increasing the bias current, but the cost is increased power dissipation. The Av is lowest and rout is highest at the bias point (i.e., VIN = VOUT = 0). rin to the stage is also lowest there. Clif Fonstad, 11/24/09 Lecture 21 - Slide 16 Specialty pairings: Push-pull or Totem Pole in Design Prob. Comments/Observations: - The D.P. output stage involves four emitter follower building blocks arranged as two parallel cascades of two emitter follower stages each. + - Driving the totem pole in this manner vIN results in a much larger output voltage range than is obtained by using a single follower as was done in our earlier examples. + 1.5 V IBIAS2 Q20 Q17 Q18 + vOUT Q21 - 50! IBIAS3 - 1.5 V NOTE: Designing with this output requires paying special attention to the biasing, and calculating the input and output resistances. Clif Fonstad, 11/24/09 The next several slides look at these aspects of the push-pull stage. Lecture 21 - Slide 17 Specialty pairings: Push-pull or Totem Pole in D.P., cont. Biasing the output stages: getting the currents right + 1.5 V IB18 = IB17 Constraint at input node: Equivalently: I " +1 (" + 1) = I E18 A Q16 IBIAS2 |IE17| - I B17 Q18 Q17 I B18 = |IB17| B Q19 IE18 p ) IE 20 = IE 21 ! Sum at emitter of Q20: Q20 IE20 IOUT = 0! I = I +I " +1 BIAS 2 |IE21| Q21 |IE21|/("p+1) IBIAS3 - 1.5 V ( E17 Constraint at output node: IE20/("n+1) IIN = 0 IB18 n 50! E 17 E 20 ( n ) ! = (" p + 1) IB17 + IE 20 (" n + 1) # & IE 20 ( = (" p + 1) % IB17 + (" n + 1)(" p + 1) ( % $ ' Sum at emitter of Q21: # & IE 21 ( IBIAS 3 = (" n + 1) IB18 + IE 21 (" p + 1) = (" n + 1) %IB18 + ! (" n + 1)(" p + 1) ( % $ ' Combining everything: IBIAS 2 IBIAS 3 = (" p + 1) (" n + 1) # " p " n Clif Fonstad, 11/24/09 ! Lesson: The bias currents are constrained. Lecture 21 - Slide 18 Specialty pairings: Push-pull or Totem Pole in D.P., cont. Biasing the output stages: getting the voltages right + 1.5 V KVL constraint: VBE 20 + VEB 21 " VBE18 " VEB17 = 0 Relating voltages to currents: A VEB17 = ( kT q) ln[ IE17 "17 IESp ] Q16 + Q20 V V EB17 + Q18 BE20 + - Q17 + V EB21 V BE18 Q21 B Q19 - 1.5 V ! VBE18 = ( kT q) ln[ IE18 "18 IESn ] VBE 20 = ( kT q) ln[ IE 20 " 20 IESn ] 50! VBE 21 = ( kT q) ln[ IE 21 " 21IESp ] Combining everything, including the fact that IESp=IESn=IES, and the results |I! |=IE20 and |IE17|/(βp+1)=IE18/(βn+1), E21 yields: IE 20 = IE18 (" p + 1) # 20# 21 (" n + 1) #17#18 Lesson: The BJT areas must be properly designed. Clif Fonstad, 11/24/09 Lecture 21 - Slide 19 ! Specialty pairings: Push-pull or Totem Pole in D.P., cont. Operation: The npn follower supplies current when the input goes positive to push the output up, while the pnp follower sinks current when the input goes negative to pull the output down. + 1.5 V + 1.5 V Load current supplied through Q 20 IBIAS2 + vIN - Q20 + vIN increases vBE20 Q17 - vBE20 increases vOUT increases In parallel + vOUT - 50! vIN decreaes + vIN - Q18 vOUT decreases vBE21 increases+ vEB21 - + Q21 50! Load current drawn out through Q 21 IBIAS3 - 1.5 V vOUT - - 1.5 V NOTE: Near vin = 0 we have two paths in parallel, and this must be considered when finding rin and rout. Clif Fonstad, 11/24/09 Lecture 21 - Slide 20 Specialty pairings: Push-pull or Totem Pole in D.P., cont. The input resistance of the output stages as seen by the Current Mirror We will make the approximation that the two emitter-follower paths can be modeled as being in parallel for purposes of calculating the input resistance. + 1.5 V A + 1.5 V Q16 Q20 2 x 50! In parallel Q18 rin2 Q21 Q17 rin1 2 x 50! - 1.5 V rin ≈ rin1|| rin2 B Q19 - 1.5 V Note: rin is smallest around vin = 0, so this is a worst-case estimate. Clif Fonstad, 11/24/09 Lecture 21 - Slide 21 Specialty pairings: Push-pull or Totem Pole in D.P., cont. The output resistance of the amplifier as seen by the 50 Ω load We will make the approximation that the two emitter-follower paths can be modeled as being in parallel for purposes of calculating the output resistance. + 1.5 V A + 1.5 V Q16 Q20 Q17 In parallel rout1 Q18 2roS2 2roS2 B - 1.5 V rout ≈ rout1|| rout2 rout2 Q21 Q19 - 1.5 V Note: rout is largest around vout = 0, so this is a worst-case estimate. Clif Fonstad, 11/24/09 Lecture 21 - Slide 22 + 1.5 V Specialty pairings: Push-pull or Totem Pole in D.P., cont. rt Q25 + vt - Reviewing the input and output resistances of an emitter follower: rin "ib ro rt rl - 1.5 V ib r! vout - IBIAS iin = i b + + "ib r! ro vin roBias roBias rl - rin = r" + (# + 1)( rl || ro || rBias ) $ r" + (# + 1) rl + it vt - rout rout = 1 [ go + gBias + (" + 1) ( r# + rt )] $ ( r# + rt ) (" + 1) Note: - Looking in the resistance is multiplied by (β+1); looking back it is divided by (β+1). ! Clif Fonstad, 11/24/09 ! Lecture 21 - Slide 23 + 1.5 V Specialty pairings: Push-pull or Totem Pole in D.P., cont. rt Q25 + vt - Reviewing the voltage gain of an emitter follower: + vout - IBIAS rl iin = i b + - 1.5 V r! vin roBias - "ib ro + rl vout = A v vin - v out = (" + 1)ib ( rl || ro || rBias ) v in = ib r# + (" + 1)ib ( rl || ro || rBias ) Av = v out (" + 1)( rl || ro || rBias ) = v in r# + (" + 1)( rl || ro || rBias ) $ (" + 1)rl r# + (" + 1) rl Note: The voltage gains of the third-stage emitter followers (Q17 and Q18) will likely be very close to one, but that of the stage-four followers might be noticeably less than one. Clif Fonstad, 11/24/09 ! Lecture 21 - Slide 24 DC off-set at the output of an Operational Amplifier: DC off-set: The node between Q12 and Q13 is a high impedance node whose quiescent voltage can only be determined by invoking symmetry.* The voltage symmetry says will be at this node. + 1.5 V The voltage on these two nodes is equal if there is no input, i.e. vIN1 = vIN2 = 0, and if the circuit is truly symmetrical/matched. Q12 Q11 Q16 ≈ - 0.4 V ≈ - 0.4 V ≈ 0 V + ≈ 0.6 V This is the high impedance node. Real-world asymmetries mean the voltage on this node is unpredictable. Q13' Q13 + ≈ 0.5 V - Q14 The voltage we need at this node to make VOUT = 0. A Q15 ≈ 0.6 V - + ≈ 0.6 V + Q18 + ≈ 0.6 V ≈ 0.6 V - Q17 Q20 + Q21 0V + vOUT - B Q19 - 1.5 V In any practical Op Amp, a very small differential input, vIN1-vIN2, is require to make the voltage on this node (and VOUT) zero. Clif Fonstad, 11/24/09 Lecture 21 - Slide 25 DC off-set at the output of an Op Amp, cont: V OUT DC off-set: The transfer characteristic, vOUT vs (vIN1 - vIN2), will not in general go through the origin, i.e., vOUT = Avd(vIN1 - vIN2) + VOFFSET 1V -A vd = 2x10 6 V IN2 - V IN1 0.5µV In the example in the figure Avd is -2 x 106, and VOFFSET is 0.1 V. V OUT -50nV 0.1V V IN2 - V IN1 R R + vIN - Input 1 - Input 2 + Clif Fonstad, 11/24/09 Avd + vOUT - In a practice, an Op Amp will be used in a feed-back circuit like the example shown to the left, and the value of vOUT with vIN = 0 will be 50 ! quite small. For this example (in which Avd = -2 x 106, and VOFFSET = 0.1 V) vOUT is only 0.1 µV. In the D.P. you are asked for this value for your design. Lecture 21 - Slide 26 Power dissipation calculation A constraint on the bias currents is the total power dissipation specification of 8.5 mW. This means that the total bias current must be ≈ 2.8 mA or less (i.e, 3 V x 2.8 mA ≈ 8.5 mW). + 1.5 V Q1 Q4 Q5 Q6 Q7 Q2 Q3 IC Q8 + vIN1 - B ID A IE Q16 Q20 Q9 IB IA Q22 Q12 Q11 A B + vIN2 - Q13 Q17 Q18 Q21 Q10 Q14 Q15 B Q19 IF + vOUT - IG - 1.5 V PQ = ( IA + IB + IC + ID + IE + IF + IG ) " 3 Volts IA + IB + IC + ID + IE + IF + IG " 2.8 mA Clif Fonstad, 11/24/09 ! Lecture 21 - Slide 27 6.012 - Microelectronic Devices and Circuits Lecture 21 - Diff-Amp Analysis II - Summary • Active loads - Lee load, Current mirror New CM analysis foils • Specialty stages - useful pairings Source coupled pairs: MOS Cascode: Postponed until Lecture 22 Push-pull output: Emitter followers in vertical chain Very low output resistance Shared duties for positive and negative output swings • Diff Amp Metrics Output resistance: Largest about zero; view as followers in parallel DC off-set on output: Nulled out by slight differential mode input Power consumption: Add up the current from the supplies Ha p p y T h a n k s g i v i n g Clif Fonstad, 11/24/09 Lecture 21 - Slide 28 MIT OpenCourseWare http://ocw.mit.edu 6.012 Microelectronic Devices and Circuits Fall 2009 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms. ...
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This note was uploaded on 11/07/2011 for the course COMPUTERSC 6.012 taught by Professor Charlesg.sodini during the Fall '09 term at MIT.

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