MIT6_012F09_lec22

MIT6_012F09_lec22 - 6.012 - Microelectronic Devices and...

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Unformatted text preview: 6.012 - Microelectronic Devices and Circuits Lecture 22 - Diff-Amp Anal. III: Cascode, µA-741 - Outline • Announcements DP: Discussion of Q13, Q13' impact. Gain expressions. • Review - Output Stages DC Offset of an OpAmp Push-pull/totem pole output stages • Specialty Stages, cont. - more useful transistor pairings The Marvelous Cascode Darlington Connection • A Commercial Op-Amp Example - the µA-741 The schematic and chip layout Understanding the circuit • Bounding mid-band - starting high frequency issues Review of Mid-band concept The Method of Open-Circuit Time Constants Clif Fonstad, 12/1/09 Lecture 22 - Slide 1 DC off-set at the output of an Operational Amplifier: DC off-set: The node between Q12 and Q13 is a high impedance node whose quiescent voltage can only be determined by invoking symmetry.* The voltage symmetry says will be at this node. + 1.5 V The voltage on these two nodes is equal if there is no input, i.e. vIN1 = vIN2 = 0, and if the circuit is truly symmetrical/matched. Q12 Q11 Q16 ≈ - 0.4 V ≈ - 0.4 V ≈ 0 V + ≈ 0.6 V This is the high impedance node. Real-world asymmetries mean the voltage on this node is unpredictable. Q13' Q13 + ≈ 0.5 V - Q14 The voltage we need at this node to make VOUT = 0. A Q15 ≈ 0.6 V - + ≈ 0.6 V + Q17 + ≈ 0.6 V Q18 - ≈ 0.6 V - Q20 + Q21 0V + vOUT - B Q19 - 1.5 V In any practical Op Amp, a very small differential input, vIN1-vIN2, is require to make the voltage on this node (and VOUT) zero. Clif Fonstad, 12/1/09 Lecture 22 - Slide 2 DC off-set at the output of an Op Amp, cont: V OUT DC off-set: The transfer characteristic, vOUT vs (vIN1 - vIN2), will not in general go through the origin, i.e., vOUT = Avd(vIN1 - vIN2) + VOFFSET 1V -A vd = 2x10 6 V IN2 - V IN1 0.5µV In the example in the figure Avd is -2 x 106, and VOFFSET is 0.1 V. V OUT -50nV 0.1V V IN2 - V IN1 R R + vIN - Input 1 - Input 2 + Clif Fonstad, 12/1/09 Avd + vOUT - In a practice, an Op Amp will be used in a feed-back circuit like the example shown to the left, and the value of vOUT with vIN = 0 will be 50 ! quite small. For this example (in which Avd = -2 x 106, and VOFFSET = 0.1 V) vOUT is only 0.1 µV. In the D.P. you are asked for this value for your design. Lecture 22 - Slide 3 Specialty pairings: Push-pull or Totem Pole Output Pairs A source follower output: - Using a single source follower as the output stage must be biased with a relatively large drain current to achieve a large output voltage swing, which in turn dissipates a lot of quiescent power. + 1.5 V Load current is supplied through Q28 as it turns on more strongly vIN goes positive + vIN - + 1.5 V Q28 v goes positive OUT + IBIAS - 1.5 V Clif Fonstad, 12/1/09 + vIN - Q + RL As Q turns off I BIAS flows through load. Turns off Negative v OUT swing limited to -I BIAS RL vOUT RL - The Problem vOUT - vIN goes negative IBIAS - 1.5 V Lecture 22 - Slide 4 Specialty Pairings: The Push-pull or Totem Pole Output A stacked pair of complementary emitter- or source-followers Large input resistance Small output resistance Voltage gain near one Low quiescent power V+ npn or n-MOS follower pnp or p-MOS follower Qn + vin+V BEn + vin-V EBp - + vout Qp - VClif Fonstad, 12/1/09 V+ + vin+V GSn RL + vin-V SGp - Qn + vout Qp - RL VLecture 22 - Slide 5 Specialty pairings: Push-pull or Totem Pole in Design Prob. Comments/Observations: - The D.P. output stage involves four emitter follower building blocks arranged as two parallel cascades of two emitter follower stages each. - Q20 and Q21 with joined sources at the output node is called a push-pull, or totem pole pair. + 1.5 V IBIAS2 Q20 + vIN - Q17 Q18 - They determine the output resistance of the amplifier. - Ideally the output stage voltage gain is ≈ 1. Clif Fonstad, 12/1/09 + vOUT Q21 - 50! IBIAS3 - 1.5 V Lecture 22 - Slide 6 Specialty pairings: Push-pull or Totem Pole in D.P., cont. Operation: The npn follower supplies current when the input goes positive to push the output up, while the pnp follower sinks current when the input goes negative to pull the output down. + 1.5 V + 1.5 V Load current supplied through Q 20 IBIAS2 + vIN - Q20 + vIN increases vBE20 Q17 - vBE20 increases - 1.5 V vOUT increases In parallel vIN decreaes + vOUT - 50! + vIN - rout ≈ rout1|| rout2 rin ≈ rin1|| rin2 Q18 vBE21 increases+ vEB21 - IBIAS3 vOUT decreases + vOUT Q21 - 50! Load current drawn out through Q 21 - 1.5 V • The input resistance, rout, is highest about zero output, and there it is the output resistance of the two follower stages in parallel. • rin is lowest at this point, too, and is a parallel combination, also. Clif Fonstad, 12/1/09 (discussed in Lecture 21) Lecture 22 - Slide 7 Specialty pairings: Push-pull or Totem Pole, cont. Voltage gain: - The design problem uses a bipolar totem pole. The gain and linearity of this stage depend on the bias level of the totem pole. The gain is higher for with higher bias, but the power dissipation is also. + 1.5 V To calculate the large signal transfer characteristic of the bipolar totem pole we begin with vOUT: vOUT = RL ("iE 20 " iE 21 ) The emitter currents depend on (vIN - vOUT): + vin+V BE20 + iE 20 = "IE 20e( v IN " vOUT ) Vt , iE 21 = IE 21e"( v IN " vOUT ) Vt ! Q20 + vout Q21 - 50! ! Clif Fonstad, 12/1/09 ( v out = RL IE 20 e( v in " v out ) Vt " e"( v in " v out ) Vt = 2 RL IE 20 sinh (v in " v out ) Vt vin-V EB21 - 1.5 V Putting this all together, and using IE21 = - IE20, we have: ! ) We can do a spread-sheet solution by picking a set of values for (vIN - vOUT), using the last equation to calculate the vOUT, using this vOUT to calculate vIN, and finally plotting vOUT vs vIN. The results are seen on the next slide. Lecture 22 - Slide 8 Voltage gain, cont.: - With a 50 Ω load and for several different bias levels we find: The gain and linearity are improved by increasing the bias current, but the cost is increased power dissipation. The Av is lowest and rout is highest at the bias point (i.e., VIN = VOUT = 0). rin to the stage is also lowest there. Clif Fonstad, 12/1/09 Lecture 22 - Slide 9 + 1.5 V Specialty pairings: Push-pull or Totem Pole in D.P., cont. rt Q25 + vt - Reviewing the voltage gain of an emitter follower: + vout - IBIAS rl iin = i b + - 1.5 V r! vin roBias - "ib ro + rl vout = A v vin - v out = (" + 1)ib ( rl || ro || rBias ) v in = ib r# + (" + 1)ib ( rl || ro || rBias ) Av = v out (" + 1)( rl || ro || rBias ) = v in r# + (" + 1)( rl || ro || rBias ) $ (" + 1)rl r# + (" + 1) rl Note: - The voltage gains of the third-stage emitter followers (Q25 and Q26) will likely be very close to one, but that of the stage-four followers might be noticeably less than one. Clif Fonstad, 12/1/09 ! Lecture 22 - Slide 10 Specialty Pairings: The Cascode Common-source stage followed by a common gate stage V+ Large output resistance Good high frequency performance Common Gate CO + V GG External Load vout - Common Source + vin IBIAS CE V- Clif Fonstad, 12/1/09 Lecture 22 - Slide 11 Specialty Pairings: The Cascode, cont. Two-Port Analysis rt iin + + v in vt Gi,cs Gm,cs v in - iout Gi,cg Go,cs Common Source A i,cg iin Go,cg + v out gel - Common Gate Gi,cs = 0, Gm ,cs = "gm ,Qcs , Go,cs = go,Qcs Gi,cg = gm,Qcg , Ai,cg = 1, Go,cg " go,Qcs Cascode two-port: rt + vt - iout iin + v in Gi,CC -! Gm,CC v in Go,CC + v out Gi,CC = 0, Gm,CC " #gm ,Qcs , Go,CC " go,Qcs Clif Fonstad, 12/1/09 gm,Qcg gel - Cascode Same Gi and Gm of CS stage, with the very much larger Go of CG. go,Qcg go,Qcg gm,Qcg Lecture 22 - Slide 12 Specialty Pairings: The Cascode, cont. Cascode two-port: rt + v in + vt - iout iin - Gi,CC Gm,CC v in Go,CC + v out gel - Cascode Gi,CC = 0, Gm,CC " #gm ,Qcs , Go,CC " go,Qcs ! go,Qcg gm,Qcg The equivalent Cascode transistor: The cascode two-port is that of a single MOSFET with the gm of the first transistor, and the output conductance of common gate. D G g QCC + v gs S Clif Fonstad, 12/1/09 d gmQ v gs cs s,b goQ cs + v ds goQ /gmQ cg cg s,b Lecture 22 - Slide 13 Specialty Pairings: The Cascode, cont. Cascode current mirrors: alternative connections Large differential output resistance Enhanced swing cascode + 1.5 V Classic Q 1 cascode Q1 Q4 Q2 Q3 Q2 Q3 + 1.5 V Q4 + 1.5 V V REF2 Q5 + vIN1 - + Q6 Wilson Q1 cascode Q2 Q3 Q4 Q7 V REF1 - 1.5 V Clif Fonstad, 12/1/09 + vIN2 - RL + vOUT - The output resistances and load characteristics are identical, but the Wilson load is balanced better in bipolar applications, and the enhanced swing cascode has the largest output voltage swing of any of them. Lecture 22 - Slide 14 Specialty pairings: Cascodes in a DP-like amplifier Comments/Observations: + 1.5 V Q1 This stage is essentially a normal source-coupled pair with a current mirror load, but there are differences.. Q2 V REF1 Q3 Q4 Q6 Q5 + vOUT - V REF2 + Q7 Q8 vIN1 - vIN2 - 1.5 V Clif Fonstad, 12/1/09 + The first difference is that two driver transistors are cascode pairs. The second difference is that the current mirror load is also cascoded. The third difference is that the stage is not biased with a current source, but is instead biased by the first gain stage. Lecture 22 - Slide 15 Specialty pairings: Cascodes in a DP-like amplifier, cont. + 1.5 V + 1.5 V Q1 QCC1 Q2 = V REF1 Q3 + vOUT - Q4 Q6 Q5 + vOUT - V REF2 + QCC2 Q7 Q8 vIN1 - + QCC1 = Q1/Q3 QCC2 = Q2/Q4 QCC3 = Q7/Q5 QCC4 = Q8/Q6 Common sources Clif Fonstad, 12/1/09 QCC3 + vIN2 - - 1.5 V vIN2 - 1.5 V + vIN1 - QCC4 Common gates g m,CC Q CC1 gm1 Q CC2 gm 2 Q CC3 gm 7 Q CC4 gm 8 g o,CC go1go 3 gm 3 go 2 go 4 gm 4 go 7 go 5 gm 5 go 8 go 6 gm 6 Lecture 22 - Slide 16 Specialty pairings: The Cascode, cont. The Folded Cascode: another variation + 1.5 V Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q7 A B Q9 B Q10 - 1.5 V Clif Fonstad, 12/1/09 Lecture 22 - Slide 17 Specialty pairings: The Darlington Connnection A bipolar pair stage used to get a large input resistance V+ Input resistance L O A D rin = 2" r# 2 = 2 " 2 gm 2 gload + Output resistance rout = 1 (1.5 go 2 + gload + gin ) Voltage gain v gm17 A v $ out = % v in 2(1.5 go 2 + gload + gin ) gin vout + vin - Q1 Q2 IBIAS V- ! Clif Fonstad, 12/1/09 Lecture 22 - Slide 18 Multi-stage amplifier analysis and design: The µA741 The circuit: a full schematic Clif Fonstad, 12/1/09 Lecture 22 - Slide 19 © Source unknown. All rights reserved. This content is excluded from our Creative Commons license. For more information, see http://ocw.mit.edu/fairuse. Multi-stage amplifier analysis and design: The µA741 Figuring the circuit out: Emitter-follower/ common-base "cascode" differential gain stage EF CB The full schematic Push-pull output Current mirror load Darlington common- emitter gain stage Clif Fonstad, 12/1/09 Simplified schematic Another interesting discussion of the µA741: http://en.wikipedia.org/wiki/Operational_amplifier Lecture 22 - Slide 20 © Source unknown. All rights reserved. This content is excluded from our Creative Commons license. For more information, see http://ocw.mit.edu/fairuse. Multi-stage amplifier analysis and design: The µA741 The chip: a bipolar IC Capacitor Resistors Transistors Bonding pads Clif Fonstad, 12/1/09 Lecture 22 - Slide 21 © Source unknown. All rights reserved. This content is excluded from our Creative Commons license. For more information, see http://ocw.mit.edu/fairuse. Mid-band, cont: The mid-band range of frequencies In this range of frequencies the gain is a constant, and the phase shift between the input and output is also constant (either 0˚ or 180˚). log |A vd | Mid-band Range !LO !b !a !d !c !LO * !HI * !HI !4 log ! ! !5 !2 1 !3 All of the parasitic and intrinsic device capacitances are effectively open circuits All of the biasing and coupling capacitors are effectively short circuits Clif Fonstad, 12/1/09 Lecture 22 - Slide 23 Bounding mid-band: frequency range of constant gain and phase Cgd g Common Source ++ v gs v rt V+ + vt in - Cgs gmv gs go gsl s,b - CO + v out gel CS gob - LEC for common source stage with all the capacitors vout - + vin - CO + d Biasing capacitors: (CO, CS, etc.) IBIAS Device capacitors: CE (Cgs, Cgd, etc.) typically in mF range effectively shorts above ωLO typically in pF range effectively open until ωHI Mid-band frequencies fall between: ωLO < ω < ωHI V- g + vt - rt + v in = v gs s,b d + gmv gs go v out - gl s,b Common emitter LEC for in mid-band range Note: gl = gsl + gel What are ωLO and ωHI? Clif Fonstad, 12/1/09 Lecture 22 - Slide 24 Estimating ωHI - Open Circuit Time Constants Method Open circuit time constants (OCTC) recipe: 1. Pick one Cgd, Cgs, Cµ, Cπ, etc. (call it C1) and assume all others are open circuits. 2. Find the resistance in parallel with C1 and call it R1. 3. Calculate 1/R1C1 and call it ω1. 4. Repeat this for each of the N different Cgd's, Cgs's, Cµ's, Cπ's, etc., in the circuit finding ω1, ω2, ω3, …, ωN. 5. Define ωHI* as the inverse of the sum of the inverses of the N ω i's: ωHI* = [Σ(ωi)-1]-1 = [ΣRiCi]-1 6. The true ωHI is similar to, but greater than, ωHI*. Observations: The OCTC method gives a conservative, low estimate for ωHI. The sum of inverses favors the smallest ωi, and thus the capacitor with the largest RC product dominates ωHI*. Clif Fonstad, 12/1/09 Lecture 22 - Slide 25 Estimating ωLO - Short Circuit Time Constants Method Short circuit time constants (SCTC) recipe: 1. Pick one CO, CI, CE, etc. (call it C1) and assume all others are short circuits. 2. Find the resistance in parallel with C1 and call it R1. 3. Calculate 1/R1C1 and call it ω1. 4. Repeat this for each of the M different CI's, CO's, CE's, CS's, etc., in the circuit finding ω1, ω2, ω3, …, ωM. 5. Define ωLO* as the sum of the M ωj's: ωLO* = [Σ(ωj)] = [Σ(RjCj)-1] 6. The true ωLO is similar to, but less than, ωLO*. Observations: The SCTC method gives a conservative, high estimate for ωLO. The sum of inverses favors the largest ωj, and thus the capacitor with the smallest RC product dominates ωLO*. Clif Fonstad, 12/1/09 Lecture 22 - Slide 26 Summary of OCTC and SCTC results log |A vd | Mid-band Range !LO !b !a !d !c !LO * !HI * !HI !4 log ! ! !5 !2 1 !3 • OCTC: 1. 2. 3. an estimate for ωHI ωHI* is a weighted sum of ω's associated with device capacitances: (add RC's and invert) Smallest ω (largest RC) dominates ωHI* Provides a lower bound on ωHI • SCTC: 1. 2. 3. an estimate for ωLO ωLO* is a weighted sum of w's associated with bias capacitors: (add ω's directly) Largest ω (smallest RC) dominates ωLO* Provides a upper bound on ωLO Clif Fonstad, 12/1/09 Lecture 22 - Slide 27 6.012 - Microelectronic Devices and Circuits Lecture 22 - Diff-Amp Analysis II - Summary • Design Problem Issues Q13, Q13'; voltage gains • Specialty stages - useful pairings Source coupled pairs: MOS Push-pull output: Two followers in vertical chain Very low output resistance Shared duties for positive and negative output swings Cascode: Common-source/emitter performance Greatly enhanced output resistance Find greatly enhanced high frequency performance also Darlington: Increased input resistance ona bipolar stage µA 741: A workhorse IC showing all of these pairs • Bounding mid-band Open Circuit Time Constant Method: An estimate of ωHI Short Circuit Time Constant Method: An estimate of ωLO Clif Fonstad, 12/1/09 Lecture 22 - Slide 28 MIT OpenCourseWare http://ocw.mit.edu 6.012 Microelectronic Devices and Circuits Fall 2009 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms. ...
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This note was uploaded on 11/07/2011 for the course COMPUTERSC 6.012 taught by Professor Charlesg.sodini during the Fall '09 term at MIT.

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