MIT6_012F09_lec25

MIT6_012F09_lec25 - 6.012 - Microelectronic Devices and...

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6.012 - Microelectronic Devices and Circuits Lecture 25 - Beyond Si; Beyond 6.012 - Outline Announcements HKN Evaluation - Do before final so you're still in a good mood. Final - Tuesday, Dec 15, 9:00 am to Noon Covering all the course; closed book; 4 problems Sub-threshold Circuit - What, Why, How Applications: medical implants, remote sensors, portable devices Digital design: choosing V DD for minimum energy per operation Devices we have known - Where are they now: MOSFETs: 5 nm Si, III-V high electron mobility transistors BJTs: InP based double heterojunction bipolar transistors LEDs: white lighting; laser diodes Solar cells: multi-junction, multi-material concentrator cells Life after 6.012 Is it possible? ( "Where does one head after taking the header?" ) Clif Fonstad, 12/10/09 Lecture 25 - Slide 1
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Sub-threshold Circuit Design: The need for low energy Emerging applications require ultra-low energy: µ -sensors, medical devices Images removed due to copyright restrictions: cartoons and figures illustrating microsensors, medical devices, ambient intelligence, and portable devices. Ambient intelligence, portable devices Sub-threshold operation: Slow, lower power, minimum energy operation becomes possible Sub-V T benefits: Power Energy Concerns: Increased sensitivity to noise and to variations in V T and T. Clif Fonstad, 12/10/09 Lecture 25 - Slide 2 Research at M.I.T. under Prof. Anantha Chandrakasan.
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Sub-threshold Circuit Design: Digital Inverters, cont. in I D out V DD = 0.3V I D = I S , s " t e v GS " V T nV t 1 " e " v DS V t # $ % % ( ( I S , s " t = KV t 2 ( n " 1) with Work of Benton H. Calhoun at M.I.T. under Clif Fonstad, 12/10/09 Lecture 25 - Slide 3 Prof. Anantha Chandrakasan's supervision. Courtesy of Benton Calhoun and Anantha Chandrakasan. Used with permission.
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Sub-threshold Circuit Design: Digital Inverters Operation of standard CMOS gate with V DD < V T CMOS Inverter Voltage Transfer Curves |V T | = 0.5 V Work of Benton H. Calhoun at M.I.T. under Clif Fonstad, 12/10/09 Lecture 25 - Slide 4 Prof. Anantha Chandrakasan's supervision. Courtesy of Benton Calhoun and Anantha Chandrakasan. Used with permission.
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Sub-threshold Circuit Design: CMOS Inverters, cont. In low-power applications an important metric the energy per operation, E pop . There is an optimum supply voltage that minimizes E pop . Operating in strong inversion, E pop = C L V DD 2 , and reducing V DD clearly reduces E pop . As V DD approaches V T , however, the contribution of sub- threshold leakage becomes important, especially because the gate delay, τ GD (time per operation) increases as charging current decreases. In general: " GD = 2 C L V DD I D , sat Only I D,sat is different depending on the region of operation. In strong inversion:
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This note was uploaded on 11/07/2011 for the course COMPUTERSC 6.012 taught by Professor Charlesg.sodini during the Fall '09 term at MIT.

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MIT6_012F09_lec25 - 6.012 - Microelectronic Devices and...

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