Lectures17_18

Lectures17_18 - Lectures 17 & 18 Fast packet switching...

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Fast packet switching Eytan Modiano Massachusetts Institute of Technology Eytan Modiano Slide 1
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Packet switches Packet Routing engine Switch Scheduler Packet Data Header Packet Tag DestinationAddress Output port number or VC number A packet switch consists of a routing engine (table look-up), a switch scheduler, and a switch fabric. The routing engine looks-up the packet address in a routing table and determines which output port to send the packet. Packet is tagged with port number The switch uses the tag to send the packet to the proper output port Eytan Modiano Slide 2
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First Generation Switches CPU LC-1 LC-2 LC-3 Input buffer output buffer Computer with multiple line cards CPU polls the line cards CPU processes the packets Simple, but performance is limited by processor speeds and bus speeds Examples: Ethernet bridges and low end routers Eytan Modiano Slide 3
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Second Generation switches Computer LC LC LC LC Bus Most of the processing is now done in the line cards Route table look-up, etc. Line cards buffer the packets Line card send packets to proper output port Advantages: CPU and main Memory are no longer the bottleneck Disadvantage: Performance limited by bus speeds Bus BW must be N times LC speed (N ports) Example: CISCO 7500 series router Eytan Modiano Slide 4
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Third generation switches N by N SWITCH FABRIC Input LC Input LC Input LC Output LC Output LC Output LC Controller Replace shared bus with a switch fabric Performance depends on the switch fabric, but potentially can alleviate the bus bottleneck Eytan Modiano Slide 5
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Switch Architectures Distributed buffer Output buffer Input buffer Eytan Modiano Slide 6
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Distributed buffer Modular Architecture Basic module is a 2x2 switch, which can be either in the through or crossed position Switch buffers: None, at input, or at output of each module Switch fabric consists of many 2x2 modules N N inputs outputs Eytan Modiano Slide 7
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Interconnection networks N input Log(N) stages with N/2 modules per stage Example: Omega (shuffle exchange network) 0 1 2 3 4 5 6 7 0 000 1 001 2 010 3 011 4 100 5 101 6 110 7 117 Notice the order of inputs into a stage is a shuffle of the outputs from the previous stage: (0,4,1,5,2,6,3,7) Easily extended to more stages Any output can be reached from any input by proper switch settings Not all routes can be done simultaneously Exactly one route between each SD pair Eytan Modiano Self-routing network Slide 8
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Self Routing Use a tag: n bit sequence with one bit per stage of the network E.g., Tag = b 3 b 2 b 1 Module at stage i looks at bit i of the tag (b i ), and sends the packet up if b i =0 and down if b i =1 In omega network, for destination port with binary address abc the tag is cba Example: output 100 => tag = 001 Notice that regardless of input port, tag 001 will get you to output 100 Eytan Modiano Slide 9
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This note was uploaded on 11/07/2011 for the course AERO 16.26 taught by Professor Dimitribertsekas during the Fall '02 term at MIT.

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Lectures17_18 - Lectures 17 & 18 Fast packet switching...

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