ME461 Prelab6 Solution - From 16MHz to 100 KHz it should be...

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1. t=0 t=Tm t=T From t =0 to t=Tm, channel A goes low while B is high, giving positive count. From t=Tm to T, channel A goes low while B is low, giving negative count. Assuming qudratureX1, channel A counts 6 positive and 4 negative, so result is 2. 2. “Dual - axis” means there are totally 4 input channels, 2 for each axis. The data bus on the LS7266 is 8 bit wide. The registers are addressed according to the most significant three bits (D7-D5), plus CD input high to specify access to registers. 3. 1 write and 3 read operations are required. They are: a) Write to RLD to reset byte pointer and move data from CNTR to OL b) Read the least significant byte c) Read the middle significant byte d) Read the most significant byte 4. Filter clock prescaler slows down the input clock as a divide on clock frequency.
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Unformatted text preview: From 16MHz to 100 KHz it should be set to 159. P2.1 and P1.4 can provide the SMCLK signal off of the chip. They should be configured as P2DIR |= 0x2; P2SEL |=0x2; P1DIR |= 0x10; P1SEL |= 0x10; 5. 6. CMR: 1011 1000 0xB8 IOR: 1100 0001 0xC1 IDR: 1110 0000 0xE0 7. a. 0xFFFFFF 0xFFFFFFFF b. 0x800000 0xFF800000 c. 0xFFFFED 0xFFFFFFED 8. Gear ratio 141:1 with quadrature X4 mode gives 564 counts per revolution. Resolution = 2*Pi/564 = 0.011 rad/count 9. t = 2 23 [cnt]/(1.5[rev/s]*564[cnt/rev]) = 9915.6 [s] = 2.75 [h] D7 D6 D5 D4 D3 D2 D1 D0 C/D X/Y RD WR CS X4,Normal Count 1 0 1 1 1 0 0 0 1 X 1 1-0-1 1-0-1 Resetting CNTR & BT 1 0 0 0 0 0 1 1 1 X 1 1-0-1 1-0-1...
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