ME461 Prelab3 Solution - assumption because this is not the...

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1. Ts_min = (Rs+Ri)*ln(2^11)*Ci = (5+2)e3*7.62*27e-12 = 1.44e-6 = 1.44 us 2. fc=5 Hz, tc = 1/fc = 0.2 us. Thus Ts_min= 1.44 [us] >= 8*tc. Without wasting unnecessary clock cycles, set ADC10CTL0 |= ADC10SHT_1 ; The theoretical maximum sampling rate should be considered together with the MSP430F2272 ADC operation timing. See section 20.2.5 “Sample and Conversion Timing”, one sampling and conversion cycle takes about 1 clock cycle to synchronize, 8 clock cycles as we just decided, and 13 clock cycle to convert. Thus, the maximum sampling rate is about f_max=5MHz/22=227 [kHz] Note: If you understand the sampling and conversion as two separate processes and assume one doesn’t affect the other, then the synchronization time and conversion time may be neglected, which gives a result of f=5MHz/8= 625[kHz]. However, you must specify your
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Unformatted text preview: assumption because this is not the real case of MSP420F2272. 3. ADC10CTL0 |= SREF_0+ADC10SHT_1+ADC10ON+ADC10IE; ADC10CTL1 |= INCH_3+SHS_0+ADC10SSEL_0; ADC10AE0 |= 0x08; 4. In Declaration: unsigned long timecnt=0; In Timer A ISR: timecnt++; if((timecnt%5)==0) ADC10CTL0 |= ENC + ADC10SC; 5. The register ADC10MEM contains the results of ADC. The quantization error in percent = (0.5*Range/(2^10)) /Range = 0.049% Read the register in ADC ISR. 6. V_ana = ADC_result *Vcc / 1023; Given V_ana = 1.25 [V], Vcc= 3.6[V], ADC_result = 355 ; Given ADC_result = 620, Vcc=3.6[V], V_ana=2.18 [V] ; 7. V = 0.00355*T + offset; T=25 C, V=1.25[V], offset = 1.25-0.00355*25 = 1.16; Thus, V = 0.003555*T + 1.16 8. V=2.5 [V], T= (2.5-1.16)/0.003555 = 377.1 [C]...
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This note was uploaded on 11/07/2011 for the course ME 461 taught by Professor Staff during the Fall '08 term at University of Illinois, Urbana Champaign.

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