ME461 Prelab3 Solution

# ME461 Prelab3 Solution - assumption because this is not the...

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1. Ts_min = (Rs+Ri)*ln(2^11)*Ci = (5+2)e3*7.62*27e-12 = 1.44e-6 = 1.44 us 2. fc=5 Hz, tc = 1/fc = 0.2 us. Thus Ts_min= 1.44 [us] >= 8*tc. Without wasting unnecessary clock cycles, set ADC10CTL0 |= ADC10SHT_1 ; The theoretical maximum sampling rate should be considered together with the MSP430F2272 ADC operation timing. See section 20.2.5 “Sample and Conversion Timing”, one sampling and conversion cycle takes about 1 clock cycle to synchronize, 8 clock cycles as we just decided, and 13 clock cycle to convert. Thus, the maximum sampling rate is about f_max=5MHz/22=227 [kHz] Note: If you understand the sampling and conversion as two separate processes and assume one doesn’t affect the other, then the synchronization time and conversion time may be neglected, which gives a result of f=5MHz/8= 625[kHz]. However, you must specify your
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