ME461_F11_PreLab2_09_11_11 - ME 461 Prelab #2 Fall 2011 Due...

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Unformatted text preview: ME 461 Prelab #2 Fall 2011 Due at the start of Lab #2 Suggested Reading: Timer A chapter in MSP430x2xx user’s guide. Lab 2 manual. 1. In your own words, explain the function of the following three lines of code. // Timer A Config TACCTL0 = CCIE; TACCR0 = 20000; TACTL = TASSEL_2 + MC_1 + ID_2; Also, what is the resulting timer clock rate (assume SMCLK is running at 16MHz)? What is the rate at which the Timer A interrupt service routine is called? 2. Suppose Timer A is sourced from SMCLK running at 16MHz. Write out the contents of the TACCR0 register for generating the following Timer A ISR rates. a. 1 kHz b. 10 kHz Hint: to achieve the following two rates you need to modify a second register. c. Period = 5ms d. Period = 25ms 3. Sketch a 10‐kHz, 20% duty cycle PWM signal. 4. Assume that TACCTL1 = OUTMOD_7 (reset/set). For each of the configurations in problem 2, write out the contents of the TACCR1 register for generating PWM duty cycles of 10%, 25%, and 80%. Also write the frequency of the PWM signal. 5. Write out the configuration necessary to provide the TA1 signal on P1.2. 6. Draw the schematic for an RC low pass filter. Choose a value for RC that results in a cutoff frequency of 150Hz. From the list of components below, choose a resistor and capacitor that best meets the cutoff frequency requirement. Resistors: 220 Ω, 470 Ω, 1 kΩ, 2.2 kΩ, 10 kΩ. Capacitors: 0.01 μF, 0.022 μF, 0.1 μF, 1.5 μF. ME 461 Prelab #2 7. Assume you filtered a 10‐kHz PWM signal through the circuit you designed above. Write the equation that relates output voltage to PWM duty cycle and compute the output voltage for duty cycles of 10%, 50%, and 90%. ME 461 Prelab #2 ...
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