Chapter5_ISA - A Closer Look at Instruction Set...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
1 CS 3401 Comp. Org. & Assembly ISA -- Chapter 5 1 A Closer Look at Instruction A Closer Look at Instruction Set Architectures Set Architectures CS 3401 Comp. Org. & Assembly ISA -- Chapter 5 2 Objectives Objectives Understand the factors involved in instruction set architecture design. Look at different instruction formats, operand types, and memory access methods. Understand memory addressing modes. Understand the inter-relation between machine organization and instruction formats to gain a deeper understanding of computer architecture in general. Understand the concepts of instruction-level pipelining and its affect upon execution performance. CS 3401 Comp. Org. & Assembly ISA -- Chapter 5 3 Instruction Formats Instruction Formats Instruction sets are differentiated by the following: Number of bits per instruction b 16, 32, and 64 bits Stack-based or register-based Number of explicit operands per instruction b 1, 2, or 3 operands Operand location b Register to register b Register to memory b Memory to memory Types and accessibility to memory of operations Type and size of operands b Numbers b Addresses b characters CS 3401 Comp. Org. & Assembly ISA -- Chapter 5 4 Design Decision for Instruction Sets Design Decision for Instruction Sets Instruction set architectures are measured according to: Main memory space occupied by a program Instruction complexity b Instruction set b The amount of decoding necessary to execute an instruction b Tasks performed by the instructions Instruction length (in bits) Total number of instruction in the instruction set
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 CS 3401 Comp. Org. & Assembly ISA -- Chapter 5 5 Design Decision for Instruction Sets Design Decision for Instruction Sets In designing an instruction set, consideration is given to: Instruction length b Whether short, long, or variable. Number of operands Number of addressable registers. Memory organization b Whether byte- or word addressable. Normally byte addressable Addressing modes. b Choose any or all: direct, indirect or indexed. How are bytes of a word stored in memory locations CS 3401 Comp. Org. & Assembly ISA -- Chapter 5 6 Little Versus Big Little Versus Big Endian Endian Byte ordering, or endianness, is another major architectural consideration. If we have a two-byte integer, the integer may be stored so that the least significant byte is followed by the most significant byte or vice versa. Little endian machines, the least significant byte is followed by the most significant byte. Big endian machines store the most significant byte first (at the lower address). CS 3401 Comp. Org. & Assembly ISA -- Chapter 5 7 Little Versus Big Little Versus Big Endian Endian As an example, suppose we have the hexadecimal number 12345678. The big endian and little endian
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 11/08/2011 for the course COMPUTER S 11111 taught by Professor Victoria during the Fall '10 term at University of Houston - Downtown.

Page1 / 12

Chapter5_ISA - A Closer Look at Instruction Set...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online