DigitalLogic

# DigitalLogic - Summary Considering the “encapsulation of...

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Unformatted text preview: Summary. Considering the “encapsulation of network in code" method, we can de— lineate certain advantages and disadvantages with respect to the “data” approach: Advantages of Code Method 1. The code method is useful for simple networks that have a fairly linear structure. With nonlinear structures such as trees, the encapsulation of the model in the code entails keeping track of branching. 2. The code method operates in a “macro expansion” fashion in that adding an extra node to the network entails adding a chunk of code to take care of that node's functional semantics. This can produce code that is faster than an interpretive method. 3. [n code, it is very straightforward to add special features that may not be available in a general-purpose network simulator that accepts a speciﬁc input format. You may, for instance, wish to perform all branching on a fork node based on the number of tokens in a previously visited server node. With the code method, this enhancement means adding one or two lines of code. With the data method, one would have to reorganize the way that the data is interpreted—41 new data ﬁeld would need to be designed. Disadvantages of Code Method 1. The code method can be unwieldy when the model is complex with possible feedback loops; it is much easier to encode by translating the graph topology directly into a data ﬁle. 2. The size of the code becomes quite complex and grows linearly with the size of the model (in terms of node number). With a data approach, it is necessary to modify the relatively compact data ﬁle without touching the code. 5.2.5 Digital Logic Circuits Let’s study the method of event scheduling by considering the digital logic circuit presented in Fig. 5.25. If we model all logic gates as having zero propagation delay. the Fig. 5.25 circuit has the behavior shown in Table 5.2. The behavior in Table 5.2 reﬂects a zero-propagation delay, for the two digital com- ponents. Time-based behavior would depend on how the inputs u 1, ug, and H3 change over time. Let’s provide input trajectories that alternate every four time units. Then the inputs and single output are seen in Fig. 5.26. We see that the behavior is such that Vt'( Y = U;). However, if we assign a propagation delay of 1 time unit to the OR gate and 2 to the AND gate, the behavior changes. First, let’s discuss the tools necessary to facilitate programming using event scheduling. The SimPack routine traceari sual (mode) is the best method of seeing the step- by-step process used by the discrete event simulator. This routine takes one argument [either INTERACTIVE or BATCH (the mode argument)], and is discuSSed in more detail in the next section. For now, we can hand simulate the digital logic circuit in Fig. 5.25 to arrive at the following procedure. The future event list (FEL) is represented as a linked list of items. Each item has a time when the eventis to occur (in parentheses) and the name of the event. Figure 5.25 Digital logic circuit. TABLE 5.2 BEHAVIOR OF FIG. 5 .25 Inputs Output 1* l “2 #3 y 0 {I 0 0 D 0 l 1 t} l 0 0 0 l l l I 0 0 0 l I) l l l l 0 1 l l 1 l 1. Schedule BEGIBLFUNC for three GEN blocks, providing the three four-time-cycle signal sources. All outputs are initialized to zero and the simulation clock is set to zero. The FEL is now {0)GEN1 —> (0)GEN2 —> (0)6EN3 . The ﬁrst event is “caused” via next -event. and event routine END_FUNC is executed for the GEN events. The code associated with GEN schedules two new events to occur to change the cycle of the signal source (i.e., to enable oscillation and to initiate an AND event). The FEL is now (0)GEN2 —) (0)GEN3 —> (2)AND —> (4)GEN1 . The blocks in the out set of the remaining two GEN blocks are now processed. This means that all blocks directly connected to the GEN blocks are scheduled since their respective outputs may change. GEN} and GEN2 cause the AND gate to be scheduled, and GEN3 causes the OR gate to be scheduled. The FEL becomes (1)0R —e {2)AND +(4)GEN1—>(4)GEN2 —> (4)GEN3 IIII' IIIDI - i - - r r . . . . I . . ...--- :||.: -....i....|....lt::g;::g1.::;, 'o'{2.3.4satanic-{2.31:5 s ‘t s 9 u I 2 3 4-5'6'1'8'9 Figure 5.26 Behavior of Fig. 5.25 TIME circuit with zero propagation delay. 4. The routine Update terminates and the next_event is processed. The simulation time is Set to l. The FEL is now (2JAND —> (4)GEN1 -—> (4}GEN2 —> (4)GEN3 5. The OR event code is executed, and the new OR block output value is determined. Then all blocks in the out set of OR are scheduled. Since there are no blocks, we go to the next step. 6. The routine Update terminates and the next_event is processed. The simulation time is set to 2. The FEL is now (ancem —» (4)GEN2 —> (4)GEN3 7. The AND event code is executed and the new AND block output value is determined. Then the OR block is scheduled to be executed at the current simulation time (2) plus the OR block delay {1}: 2 +1 = 3. This general procedure is executed repeatedly until the simulation time is exhausted. The algorithm for the block simulator with event scheduling is shown below. Algorithm 5.5. Block Simulator Using Event Scheduling Procedure Main Set SIMCLOCK to zero Read in block network structure Initialize at! output black values For each Generator Block, schedule GEN While more simulation time do Get next event Update End White End Main Procedure Update Update SIMCLOCK For event GEN: Generate an mediating square wave Schedule GEN at SIMCLOCK + detayfonwave For aii other events: Given inputs saved. execute the function associated with this block For aii events: Save the inputs of all blocks in the out set of this block Schedule out set biocks to occur using their delay times and stored inputs End Update The input data for a general digital logic network is #blocks #outputbloek time block-mun block—type delay input-.1 inputz #outputs outputl param1 param2 block-mum block—type delay inputl input-.2 #outputs outputl param1 param2 This format is very similar to that of the time slicing simulator with the exception that, here, we specify the out set of each block (Table 5.3). First, running the event scheduling simulator with zero propagation delays for the and and or gates with input 5 4 18.0 gen 0.0 1 3 gen 0.0 l 3 gen 0.014 and 0.00114 or 0.0 3 2 1 5 bme0 yields the same behavior as in Fig. 5.25. If we let an and gate take 2 time units delay. and an or gate take 1 time unit delay, we can employ the event scheduling method as follows. Using the code for the simulator, and inputting the data 4 18.0 gen 0.0 1 3 gen 0.0 1 3 gen 0.0 l 4 and 2.0 0 1 l 4 or 1.0 3 2 1 5 thumb-JUL" we obtain Fig. 5.27. The digital logic simulator provides a tool for basic logic simulation. For inputs to the same block, where event times are equal, duplicate events (equal times and block id} arise. In such a case, the last such event will contain the accurate input information for the block to execute. The future event list can be trimmed when duplicate events arise. TABLE 5.3 BLOCK DEFINITIONS .._._—.______—_—__ Type Symbol Description Input] Input2 Param.i Farm. 2 gen GEN generator NM NA NA NRA and AND and-gate inputl inputz NI’A NIA nand NAND nand—gate input I input2 NM NM or OR or—gate input I input2 NA NA not NOR nor—gate input I input2 NM NM inv INV inverter in put 1 NA NA NIFA I I I I I I I l I I I I I I- I I I I I I I I I '0-1- '3 45 67-359 I | I 2 '1'23-4'5'6I753?9?0!II2'3!4! Is I I I I I I I I I I I I I I I I I I I I I I I I I I I J I I I I TIME Figure 5.27 Behavior of Fig. 5.25 logic circuit with nominal delays. 5.2.6 Queuing Models Queues occur in many physical systems, from lines at fast-food restaurants to waiting lines of computer jobs awaiting service from a processor. To model queuing systems, we will require the basic event scheduling method of the preceding section, but in addition we will need special tools for handling lines that occur at multiservice stations. Primitive queuing scenarios may be modeled using only the tools that we presented in the preceding section; however, when modeling queuing systems we also want to be concerned with special features such as (1} jockeying from one queue to another and (2) allowing queue entities to be assigned speciﬁc attributes and priorities. First, let’s discuss some key statistics that will be of concern to us when reviewing the simulation output of a queuing system. a Givens. Let T = total time for simulation (600 for our example), A = number of arrivals (6 customers into the bank), and C = number of completions. We will assume that A = C. The two will converge given a long simulation and relatively short queueing times (ﬂow balance assumption}. 0 fig-rival Rate. A 2 AN". 0 Throughput Ra X = Cf T. If we let A = C, then A = X. An important note about it and X: they are relative measures. When you say that the throughput of an operating system, for instance, is 5 jobs per hour. you cannot accurately gauge ...
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## This note was uploaded on 11/09/2011 for the course CAP 4800 taught by Professor Fishwick during the Fall '08 term at University of Florida.

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DigitalLogic - Summary Considering the “encapsulation of...

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