Lab 6 Logic Gates and Flip Flops

Lab 6 Logic Gates and Flip Flops - Objective: To...

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Objective: To investigate the characteristics of TTL NAND gates and to examine circuits utilizing TTL NAND gates as well as J-K flip-flops. Requirements: Figures: Procedure: Then NAND Gate: 1. Apply power and ground to the appropriate pins of the 7400 IC. Select any one of the four NAND gates, connect the dip switch to each input, and connect the output to a logic indicator on the designer box. Fill out the truth table using the multimeter to measure the voltage and determine the state of both inputs. Use the LED to indicate the logic level of the output voltage. Truth Table A B F 0 0 1 0 1 1 1 0 1
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1 1 0 2. Build the inverter circuit of figure 8 using the 0-5 volt, 1000 Hz square wave from the bench function generator to supply. Connect the scope to both the input and output and sketch the two waveforms below. 1000 Hz Square-Wave inverter circuit 3. Let input A “float” by disconnecting it from the 5 volt source. How does this output change? The output does not change when you let A ”float”.
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This note was uploaded on 11/14/2011 for the course EE 361 taught by Professor Most during the Winter '08 term at Cal Poly.

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Lab 6 Logic Gates and Flip Flops - Objective: To...

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