Lab 6 part 2 (1)

Lab 6 part 2 (1) - Purpose: To investigate the...

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Purpose: To investigate the characteristics of a J-K flip-flop. Requirements: Figures: Procedure: 1. Apply power and ground to the appropriate pins of the 74107 IC. Using either flip-flop, connect the J, and K inputs to dip switches, the CLK input to logic switch Ā, and the CLR input to logic switch B(bar). Also, connect the J, K, Q and Q to logic indicators. Momentarily ground the CLR input (close logic switch B(bar)) to set Q to zero. Fill in the Truth table by performing the following procedure: a. Apply low levels to J and K (0,0), and apply a clock pulse (momentarily close switch Ā). b. Repeat this procedure (step a) for all combinations of J and K in the truth table below. Truth Table for 74107 IC J K Q Q(bar) 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 2. Build the frequency divider circuit of figure 11 using either flip-flop (remember to keep CLR connected to B(bar)). Using the pulse generator, apply a 0 to 4 volt, 400 Hz pulse with a width of 2 ms to the clock input. Note that this signal has a period of 2.5 ms, and the 2 ms pulse width
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This note was uploaded on 11/14/2011 for the course EE 361 taught by Professor Most during the Winter '08 term at Cal Poly.

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Lab 6 part 2 (1) - Purpose: To investigate the...

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