20 - 20-Oct-119:25 AM1University of Florida, EEL 3701 File...

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Unformatted text preview: 20-Oct-119:25 AM1University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzIntro to VHDLEEL 37011University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzEEL 3701Menu VHDL VHDL: The EntityVHL: IEEE 1076 TYPEVHDL: IEEE 1164 TYPEVHDL: The ArchitectureMixed-Logic in VHDLVHDL MUX examplesLook into my ...See examples on web-site: (VHDL Examples) NAnd2a.vhd,NAnd2b.vhd,Mux2to1*.vhd, * = a-f, Mux41*See also example file on web: Creating graphical components (Component_Creation.pdf)EEL 37012University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzEEL 3701Introduction to VHDL Q: What is VHDL? A: VHSICHardware Description Language Q: What is VHSIC? A: Very High Speed Integrated Circuits Q: What is VHDL used for? A: To describe and test a digital circuit in a high level language environment. When used in conjunction with a router and logic generator a silicon mask can be created. A competitor to VHDL is Verilog(older and more widely used until recently, but ...)20-Oct-119:25 AM2University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzIntro to VHDLEEL 37013University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzEEL 3701VHDL Syntax VHDL is case insensitive>GOOD = Good= good = gOOD Everyone has their own conventions; mine follows:> Keyword of VHDL are all lower case> Entity and architecture names are all upper case> Identifiers start with a capital> All new words in a given identifier is again capitalized White space (spaces or tabs) is fine anywhere as separators The semicolon is a statement terminator Two dashes (--) indicate a comment follows Identifiers must begin with a letter; subsequent characters are alphanumeric or _ No precedence in VHDL; resolves left-to-right; useparen.(except nothas precedence over logical operators)EEL 37014University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzEEL 3701VHDL: The EntityentityNAND2a isport(A,B: in bit;C: out bit);end NAND2a; Example:Black BoxThe entity is the description of inputs and outputs to a black boxentity BLACK_BOX is port(Clock, Reset: inbit;D:inbit_vector(7 downto 0);Q:out bit_vector(7 downto 0);CO:out bit);end BLACK_BOX;20-Oct-119:25 AM3University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzIntro to VHDLEEL 37015University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzEEL 3701VHDL: The EntityEntity syntax:entityNAND2a isport(A,B: in bit;C: out bit);end NAND2a;entity ENTITY_NAME is port(-- optional parameterized componentsName1: mode type;Name2: mode type;NameN: mode type);end ENTITY_NAME; Names can be a list of names separated by commas (as in the NAND2a above right) Modes describe data direction flow Types indicate the set of values the port name can be assignedEEL 37016University of Florida, EEL 3701 File 20 Dr. Eric M. SchwartzEEL 3701 Ports are often associated with pins Ports are a special class of something called a...
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20 - 20-Oct-119:25 AM1University of Florida, EEL 3701 File...

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