21 - 20-Oct-11—9:31 AM1University of Florida EEL 3701 –...

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Unformatted text preview: 20-Oct-11—9:31 AM1University of Florida, EEL 3701 – File 21© Drs. Eric M. SchwartzPLDs, CPLDsEEL 37011University of Florida, EEL 3701 – File 21© Dr. Eric M. SchwartzEEL 3701Menu• Programmable Logic Devices (PLDs)>Programmable Array Logic (PALs)>Programmable Logic Arrays (PLAs)• PAL/GAL 16V8• CPLD: Altera’s MAX 7064 and MAX 3064Look into my ...See examples on web:Lam Ch 6 PLD figs, PAL/GAL info, m7000.pdf, m3000a.pdf, (specs on MAX 7064, 3064)• Read Roth: Sections 9.6-9.8(Sections 16.4-16.6)• (Optional) Read Lam: Sections 6.4EEL 37012University of Florida, EEL 3701 – File 21© Dr. Eric M. SchwartzEEL 3701Programmable Logic Devices and Programmable Logic Arrays (PLA’s)• In conventional MSOP design, a function of 10 inputs and 8 outputs can be expressed as: > Zi= f (x, x1, ... , x9), i = 0, 1, ... , 7 See Lam Section 6.4XX1X2X3 X4X5X6X7X8X9ZZ1Z2Z3 Z4Z5Z6Z7Xi’sZi...............20-Oct-11—9:31 AM2University of Florida, EEL 3701 – File 21© Drs. Eric M. SchwartzPLDs, CPLDsEEL 37013University of Florida, EEL 3701 – File 21© Dr. Eric M. SchwartzEEL 3701PLD Shorthand NotationLAM Fig 6.9EEL 37014University of Florida, EEL 3701 – File 21© Dr. Eric M. SchwartzEEL 3701LAM Fig 6.10PLAExample Simplified SchematicsPLA20-Oct-11—9:31 AM3University of Florida, EEL 3701 – File 21© Drs. Eric M. SchwartzPLDs, CPLDsEEL 37015University of Florida, EEL 3701 – File 21© Dr. Eric M. SchwartzEEL 3701Simplified SchematicsLAM Fig 6.11PLAEEL 37016University of Florida, EEL 3701 – File 21© Dr. Eric M. Schwartz© Dr....
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  • Fall '08
  • LAM
  • Logic gate, Programmable logic device, Programmable logic array, Programmable Array Logic, Dr. Eric M. Schwartz, Eric M. Schwartz

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21 - 20-Oct-11—9:31 AM1University of Florida EEL 3701 –...

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