alu - Date: November 10, 2010

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Date: November 10, 2010 //mil.ufl.edu/ems/eel/3701/gcpu/gcpu-f10/alu/alu.bdf Project: computer Debug Signals 0 0 0 1 REGB 0 0 0 0 REGA 0 0 1 0 Sum(A,B) 0 1 0 0 OR(A,B) 0 0 1 1 AND(A,B) 0 1 1 1 SHFA_Left 0 1 0 1 COMA 0 1 1 0 COMB 1 0 0 1 SHFB_Left 1 0 0 0 SHFA_Right 1 0 1 0 SHFB_Right __________________ MSC3:0 Selection Negate B Negate A OR Generation AND Generation Mux A, Mux B, Reg A, Reg B Block Mux C Block fs REGA0 MSA0 REGB0 CLK MSB1 MSB0 CLK MSA1 B1 1 REGB1 CLK REGA1 CLK /RESET /RESET REGB2 CLK MSB1 MSB0 REGA2 CLK MSA1 MSA0 A3 REGB3 B3 REGA3 CLK CLK GD MSC3 GD MSC3 GD MSC3 MSC3 GD OUT3 OUT2 OUT1 OUT0 GD MSC3 GD MSC3 GD MSC3 GD MSC3 OUT7 OUT6 OUT5 OUT4 A2 A0 B2 B0 OUT2 REGB2 REGA2 REGB3 REGA3 DATA3 OUT3 DATA2 OUT2 REGB2 REGA2 REGB3 REGA3 DATA3 OUT3 DATA2 OUT0 REGB0 REGA0 REGB1 REGA1 DATA1 OUT1 DATA0 OUT0 REGB0 REGA0 REGB1 REGA1 DATA1 OUT1 DATA0 /RESET /RESET /RESET /RESET /RESET /RESET MSC1 MSC2 REGB4 SUM4 REGA4 MSC0 AND4 OR4 NEGA4 NEGB4 REGA3 REGA5 REGB3 REGB5 MSC1 MSC2 REGB5 SUM5 REGA5 MSC0 AND5 OR5 NEGA5 NEGB5 REGA4 REGA6 REGB4 REGB6 MSC1 MSC2 REGB6 SUM6 REGA6 MSC0 AND6 OR6 NEGA6 NEGB6 REGA5
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This note was uploaded on 11/12/2011 for the course EEL 3701 taught by Professor Lam during the Fall '08 term at University of Florida.

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