controller - Date: November 10, 2010

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Unformatted text preview: Date: November 10, 2010 //mil.ufl.edu/ems/eel/3701/gcpu/gcpu-f10/controller/controller.bdf Project: computer Q2 Q3 Q1 Q0 IR3 IR4 IR2 IR0 IR1 NEG_FLAG ZERO_FLAG IR5 Q5 D5 CLK /RESET Q4 CLK D4 /RESET Q3 CLK D3 /RESET Q2 D2 CLK /RESET Q1 D1 CLK /RESET Q0 CLK /RESET D0 DATA31 DATA30 DATA29 DATA28 DATA27 DATA26 DATA25 DATA24 DATA23 DATA22 DATA21 DATA20 DATA19 /IR_LD DATA18 DATA16 DATA15 DATA14 DATA13 DATA12 DATA11 /PC_LD_LOWER DATA10 DATA8 /MAR_LD_LOWER /MAR_LD_UPPER /X_LD_LOWER /X_LD_UPPER /Y_LD_LOWER /Y_LD_UPPER DATA1 DATA0 DATA[31..0] MCLK /PC_LD_UPPER XD_LD YD_LD ADDR_SEL1 ADDR_SEL0 Y_INC MAR_INC X_INC PC_INC R_/W MSC1 MSC0 MSC2 MSB0 MSC3 MSB1 MSA1 MSA0 D1 D0 D2 D4 D3 D5 ADDRESS0 ADDRESS1 ADDRESS2 ADDRESS3 ADDRESS4 ADDRESS5 ADDRESS6 ADDRESS7 ADDRESS8 ADDRESS10 ADDRESS9 ADDRESS11 ADDRESS[13..0] ADDRESS13 ADDRESS12 Q5 Q4 DATA3 DATA2 DATA4 DATA5 DATA6 DATA7 DATA9 DATA17 Controller Input & Output Debug Purposes Controller Inputs (State, Flags, Instruction) ASM State Generation Controller Outputs...
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This note was uploaded on 11/12/2011 for the course EEL 3701 taught by Professor Lam during the Fall '08 term at University of Florida.

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