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cpu - .0 OUTPUT Y[15.0 OUTPUT PC[15.0 OUTPUT X[15.0 OUTPUT...

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Date: November 10, 2010 //mil.ufl.edu/ems/eel/3701/gcpu/gcpu-f10/cpu/cpu.bdf Project: computer Data Bus Tri-State Creation Instruction Register (IR) Program Counter (PC) & Memory Address Register (MAR) & Index Regs (X,Y) CPU ASM Controller Arithmetic Logic Unit (ALU) MSA[1..0] MSB[1..0] MSC[3..0] PC_INC /PC_LD_LOWER /PC_LD_UPPER MAR_INC /MAR_LD_LOWER /MAR_LD_UPPER X_INC /X_LD_LOWER /X_LD_UPPER Y_INC /Y_LD_LOWER /Y_LD_UPPER /IR_LD R_/W ADDR_SEL1 ADDR_SEL0 XD_LD YD_LD STATE[5..0] CLK /RESET ZERO_FLAG NEG_FLAG IR[5..0] MCLK R_/W CLK /RESET DATA[5..0] /IR_LD IR[5..0] CLK /RESET MSA[1..0] MSB[1..0] MSC[3..0] DATA[7..0] ZERO_FLAG NEG_FLAG ALU[7..0] A[7..0] B[7..0] /MAR_LD_LOWER /MAR_LD_UPPER ADDR_SEL0 ADDR_SEL1 XD_LD YD_LD ADDR[15..0] PC[15..0] X[15..0] MAR[15..0] Y[15..0] YDISP[7..0] XDISP[7..0] CLK /RESET DATA[7..0] PC_INC /PC_LD_LOWER /PC_LD_UPPER X_INC /X_LD_LOWER /X_LD_UPPER Y_INC /Y_LD_LOWER /Y_LD_UPPER MAR_INC ALU[7..0] DATA[7..0] VCC /RESET INPUT VCC CLK INPUT VCC MCLK INPUT MSC[3..0] OUTPUT NEG_FLAG OUTPUT ZERO_FLAG OUTPUT YDISP[7..0] OUTPUT XDISP[7..0] OUTPUT /IR_LD OUTPUT ADDR_SEL[1..0] OUTPUT ALU[7..0]
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Unformatted text preview: .0] OUTPUT Y[15. .0] OUTPUT PC[15. .0] OUTPUT X[15. .0] OUTPUT MAR[15. .0] OUTPUT B[7. .0] OUTPUT A[7. .0] OUTPUT R_/W OUTPUT ADDR[15. .0] OUTPUT VCC DATA[7. .0] BIDIR NOT 73 CLK /RESET ZERO_FLAG NEG_FLAG IR[5. .0] MCLK MSA[1. .0] MSB[1. .0] MSC[3. .0] PC_INC /PC_LD_LOWER /PC_LD_UPPER MAR_INC /MAR_LD_LOWER /MAR_LD_UPPER X_INC /X_LD_LOWER /X_LD_UPPER Y_INC /Y_LD_LOWER /Y_LD_UPPER /IR_LD R_/W ADDR_SEL1 ADDR_SEL0 XD_LD YD_LD Q[5. .0] ADDRESS[13. .0] DATA[31. .0] controller inst4 CLK /RESET DATA[7. .0] PC_INC /PC_LD_L /PC_LD_U X_INC /X_LD_L /X_LD_U Y_INC /Y_LD_L /Y_LD_U MAR_INC /MAR_LD_L /MAR_LD_U ADDR_SEL0 ADDR_SEL1 XD_LD YD_LD ADDR[15. .0] PC[15. .0] MAR[15. .0] X[15. .0] Y[15. .0] XDISP[7. .0] YDISP[7. .0] pc_mar_ix inst5 CLK /RESET MSA[1. .0] MSB[1. .0] MSC[3. .0] DATA[7. .0] OUT[7. .0] NEG_FLAG ZERO_FLAG REGA[7. .0] REGB[7. .0] alu inst6 CLK /RESET /IR_LD DATA[5. .0] IR[5. .0] ir inst7 TRI 65...
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