ex2_s10 - University of Florida Department of Electrical...

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University of Florida EEL 3701—Spring 2010 Dr. Eric M. Schwartz Department of Electrical & Computer Engineering Monday, 29 March 2010 Page 1/ 11 Exam 2 ____________________________ Last Name , First Name Good luck & Go Gators!!! Instructions: Turn off all cell phones , beepers and other noise making devices . Show all work on the front of the test papers. Box each answer. If you need more room, make a clearly indicated note on the front of the page, "MORE ON BACK", and use the back. The back of the page will not be graded without an indication on the front. You may not use any notes, HW, labs, other books, or calculators. This exam counts for 22% of your total grade. Read each question carefully and follow the instructions . You must pledge and sign this page in order for a grade to be assigned. The point values for problems may be changed at prof’s discretion. Put your name at the top of this test page (and, if you remove the staple, all others). Be sure your exam consists of 11 distinct pages. Sign your name and add the date below. For each circuit design, equations must not be used as replacements for circuit elements. For each mixed-logic circuit diagram, label inputs of each gate with the appropriate logic equations Boolean expression answers must be in lexical order ,( i.e., /A before A, A before B, & D 3 before D 2 ). Label the inputs and outputs of each circuit with activation-levels. For K-maps, label each grouping with the appropriate equation. PLEDGE: On my honor as a University of Florida student, I certify that I have neither given nor received any aid on this examination, nor I have seen anyone else do so. SIGN YOUR NAME DATE ( 29 March 2010 ) Page Available Points 2-3 14 4 13 5 13 6 10 7 11 8-9 20 10-11 19 TOTAL 100 Regrade comments below: Give page # and problem # and reason for the petition. Good Evening! Welcome!
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University of Florida EEL 3701—Spring 2010 Dr. Eric M. Schwartz Department of Electrical & Computer Engineering Monday, 29 March 2010 Page 2/ 11 Exam 2 ____________________________ Last Name , First Name [14%] 1. Design a system that sequences through the following outputs: 3, 7, 0, 1, 3, 7, 0, etc. The system must asynchronously reset to output the “ 3 ” when Start (active-low) goes true. When the sequence output is 7, the active-low output Z should be true. Use a JK-FF for the most significant bit of the design, a T-FF for the least significant bit, and a D-FF for any other bits you might need. Note: All the given FFs have active-low asynchronous clear and set inputs. Use the minimum number of flip-flops and the minimum number of other SSI gates necessary to solve this problem. a) Complete the next-state truth table. You may not need all the rows and/or columns. b) Find the required simplified (MSOP or MPOS) equations.
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This note was uploaded on 11/12/2011 for the course EEL 3701 taught by Professor Lam during the Fall '08 term at University of Florida.

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ex2_s10 - University of Florida Department of Electrical...

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