G-CPU_Block_Diagram - Z Flag N Flag MUXC MSA1:0 MSB1:0...

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University of Florida EEL 3701 Drs. Gugel and Schwartz Revision 0 10-Nov-10 Page 1/1 G-CPU Block Diagram P rogram C ounter (H/L) Bi-directional Data Bus IR_LD CLK Controller IR5:0 CLK PC_INC PC_LD (U/L) Z Flag MAR_INC MAR_LD (U/L) N Flag X_INC X_LD (U/L) Y_INC Y_LD (U/L) IR_LD R/-W ADDR_SEL1:0 XD_LD YD_LD MUXA MUXB ALU
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Unformatted text preview: Z Flag N Flag MUXC MSA1:0 MSB1:0 MSC3:0 CLK R/-W IR5:0 Register R/-W Address Bus Mux 1 2 3 S1 S0 6 A15:0 ADDR_SEL1:0 M em A ddr R eg (H/L) X Reg Block Y Reg Block Note: PC, MAR, X, Y outputs are 16 bits X Reg Block = X displacement Reg + X Reg (H/L) Y Reg Block = Y displacement Reg + Y Reg (H/L) (Reset not shown due to space constraints)...
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This note was uploaded on 11/12/2011 for the course EEL 3701 taught by Professor Lam during the Fall '08 term at University of Florida.

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