Unformatted text preview: University of Florida EEL 3701 Dr. Eric M. Schwartz Department of Electrical & Computer Engineering HOMEWORK 2 6-Sep-11 Page 1/1 Revision A(L) B(H) C(L) D(H) X(L) Note: Late HW is not accepted! HW is due at the beginning of class. Put your “last name, first name” and the HW number in the top right hand corner of the first page of all HW assignments. Staple your pages together. Do not put your social security number or your UF ID number on your HW. 1. Design the logic diagrams (by hand) for the following logic equations using only AND (no bubbles), OR (no bubbles) and NOT gates of any sizes desired. Assume the inputs and outputs are all active- high. (Do not reduce the expression before implementing.) Always assume that you should try to minimize the number of gates required unless some other optimization criteria is specified. Logic Equations: a) X = /(/A + B) * (B + /C) b) Y = (A +/B) * /(/B*/C + B*C) 2. Repeat 1a & 1b but this time assume that you can select the activation level of all signals and you can 2....
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This note was uploaded on 11/12/2011 for the course EEL 3701 taught by Professor Lam during the Fall '08 term at University of Florida.
- Fall '08