lab6_f11_alu_cpu - University of Florida Department of...

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University of Florida EEL 3701 — Fall 2011 Dr. Eric M. Schwartz Department of Electrical & Computer Engineering Revision 0 12-Oct-11 Page 1/4 LAB 6: Arithmetic Logic Unit (Element of a CPU) OBJECTIVES The objective of this lab is to design and augment a simple arithmetic logic unit (ALU) with registers and several multiplexers to create a simple central procession unit (CPU). This device will perform simple addition, logical complement, logical AND, logical OR and shifting of 4-bit data. MATERIALS Prototype Board, Wires, Switches, LEDs and UF-3701 CPLD Board Useful Quartus Components: In “others | maxplus2” library o 74153: Two 4-input MUX’s (recommended) o 74151: 8-input MUX (recommended) o 74283: 4-bit Adder (recommended) o 7474: Dual D-FF (not recommended) o 74175: Quad D-FF (not recommended) In “megafunctions | gates” library o mux (not recommended) o lpm_mux (not recommended) In “primitives | storage” library o dff (recommended) In “primitives | logic” library o not, and2, or2, bor2, etc. In “primitives | pin” library o input, output In “primitives | other” library o vcc, gnd INTRODUCTION A block diagram of the CPU you will design is shown in Figure 1. 1. The device has one 4-bit wide INPUT bus and one 4-bit wide OUTPUT bus. These buses are used to bring data to and from the ALU. The OUTPUT bus is fed back for possible re-entry to the system. 2. REG A and REG B are 4-bit wide registers (i.e., 4 D Flip-Flops) that are used to hold data originating from MUX A and MUX B. MUX A & B (each containing four 4-input multiplexers) are used to connect a particular bus to REG A and REG B. A bus is connected as described in Table 1. The outputs of REGA and REGB are thus fed back to MUX A and MUX B inputs as well as to a combinatorial logic block. The signals REGA and REGB are system outputs. The combinatorial logic block is used to perform data complement, addition, ORing, ANDing, and shifts. 3. MUX C consists of four 8-input multiplexers. They are used to select a particular operation for outputs. The three select lines MSC2:0 function as shown in Table 2 (where the most significant bit is on the left). 4. The carry output, Cout, should come directly from the adder circuit (with no additional circuit necessary). COMPILATION AND SIMULATION
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This note was uploaded on 11/12/2011 for the course EEL 3701 taught by Professor Lam during the Fall '08 term at University of Florida.

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lab6_f11_alu_cpu - University of Florida Department of...

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