lab8_f11_cpu_design - EEL 3701 Fall 2011 University of...

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University of Florida EEL 3701 — Fall 2011 Dr. Eric M. Schwartz Department of Electrical & Computer Engineering 21-Oct-11 Page 1/5 Revision 0 LAB 8: Elementary CPU Design: Fetching Instructions From a ROM OBJECTIVE The objective of this lab is to continue the design of an elementary central processing unit (CPU) that was started in Lab 4 and Lab 6. In part 1 of this lab, a 2-bit instruction field will be used to control a simple state machine that in turn will be used to set the MUX lines in the ALU according to what type of instruction is designated for execution. In part 2, a 3-bit instruction field will be used. You will also add a program counter (PC) and a memory module to store the instructions of a “program” to be executed by the CPU. MATERIALS Your UF-3701 board, Prototype Board, Wires, Switches, LEDs (including your debounced switch circuit) One 28256 EEPROM, supplied in lab (for lab use only) INTRODUCTION - LAB 6 ALU MUX SIGNALs The ALU designed in Lab 6 consisted of (4) 4:1 MUXs on the inputs of REGA and (4) 4:1 MUXs on the inputs of REGB. The select lines for these MUXs were designated MSA1:0 and MSB1:0, respectively. For a quick review, the MUXs selected a bus as shown in Table 1. The outputs of REGA and REGB were then passed to a combinatorial logic block and the results of this were then passed to (4) 8:1 MUXs. The select lines for these (4) MUXs were designated as MSC2:0. For review purposes, these (3) lines selected the functions shown in Table 2. Modify your lab 6 ALU design only if it did not work. We’ll call this the Lab 6* ALU . PART 1 INTRODUCTION: 1 st ALU CONTROLLER A state machine controller and Instruction Register (IR) are now added to the Lab 6* ALU to facilitate the execution of simple instructions. See Figure 1 for the total system components of this section. The IR register contains 2 bits that represent the four instructions shown in Table 3. The flowchart ( NOT an ASM) for the controller is shown in Figure 2. All instructions execute in one cycle (plus one cycle to load the IR register). I strongly encourage you to use VHDL for the combinatorial part of the controller. Instruction Register Design The IR is clocked like a typical bank of D Flip-Flops, however, it has a new feature; it can be loaded or not loaded depending on “IR.LD”. When IR.LD is true, data is loaded into the register and when IR.LD is false, new data is not loaded into the register (hold condition). This register can be simply realized with a 2:1 MUX on the input of each flip-flops of the IR. When a 2:1 MUX select line is low, select an IR output to pass through the MUX back into a D- FF input; when the select line is high, an INPUT bus signal should pass through a MUX and into a D-FF input. PART 1 PRE-LAB REQUIREMENTS
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This note was uploaded on 11/12/2011 for the course EEL 3701 taught by Professor Lam during the Fall '08 term at University of Florida.

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lab8_f11_cpu_design - EEL 3701 Fall 2011 University of...

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