pc_mar_ix -...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
Date: November 10, 2010 //mil.ufl.edu/ems/eel/3701/gcpu/gcpu-f10/pc_mar_ix/pc_mar_ix.bdf Project: computer Y Index Register X Index Register Memory Address Register Program Counter Register Y Displ. Generation X Displ. Generation Address Selection/Generation Input / Output Signals 0 0 PC Register 0 1 MAR Register 1 1 Y + Displ. 1 0 X + Displ. ____________________________ ADDR_SEL1:0 Addr Output Debug Signals YD_LD /RESET XD_LD CLK DATA[7. 0] DATA1 DATA0 DATA2 /PC_LD_L /RESET DATA3 CLK /PC_LD_L DATA4 DATA6 DATA5 DATA7 /RESET CLK DATA0 /PC_LD_U DATA1 DATA3 DATA2 CLK /RESET /PC_LD_U DATA5 DATA4 DATA7 DATA6 CLK /RESET Y0 X0 YA3 YA2 YA1 YA0 Y2 YDISP1 Y1 YDISP0 XA3 XA2 XA1 XA0 X2 XDISP1 X1 XDISP0 YDISP3 Y3 YDISP2 XDISP3 X3 XDISP2 Y4 X4 YA7 YA6 YA5 YA4 Y6 YDISP5 Y5 YDISP4 XA7 XA6 XA5 XA4 X6 XDISP5 X5 XDISP4 YDISP7 Y7 YDISP6 XDISP7 X7 XDISP6 Y8 X8 YA11 YA10 YA9 YA8 Y10 Y9 XA11 XA10 XA9 XA8 X10 X9 Y11 X11 Y12 X12 YA15 YA14 YA13 YA12 Y14 Y13 XA15 XA14 XA13 XA12 X14 X13 Y15 X15 PC12 MAR12 PC8 MAR8 PC4 MAR4 PC0 MAR0 ADDR12 YA12 XA12 ADDR_SEL1 ADDR_SEL0 ADDR8 YA8 XA8 ADDR_SEL1 ADDR_SEL0 ADDR4 YA4 XA4 ADDR_SEL1 ADDR_SEL0 ADDR0 YA0 XA0 ADDR_SEL1 ADDR_SEL0 ADDR13 MAR13 XA13 PC13 YA13 ADDR9 MAR9 XA9 PC9 YA9 ADDR5 XA5
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 11/12/2011 for the course EEL 3701 taught by Professor Lam during the Fall '08 term at University of Florida.

Ask a homework question - tutors are online