rom_creation - University of Florida EEL 3701 Drs Eric M...

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University of Florida EEL 3701 Drs. Eric M. Schwartz & Karl Gugel Department of Electrical & Computer Engineering Revision 0 21-Oct-11 Page 1/3 Quartus ROM Creation Instructions 1 Figure 1: An lpm_rom component. address[9..0] clock q[7..0] lpm_rom0 inst Figure 2: ROM with signals named and defined. Problem: You have an ASM or CPU that you would like to control/test from an EEPROM. How can you simulate the EEPROM under Quartus? Solution: Use the ROM model found in the “megafunctions | storage” library called “lpm_rom.” Unfortunately, Quartus no longer supports asynchronous memory devices with Quartus or their new devices. Therefore, we will have to add a clock that is not needed in the actual EEPROM. Design Procedure: 1. Create a new project and BDF file (File- >New…). I called mine rom_1kx8 and my rom_1kx8.bdf, respectively. 2. For the device family, pick something that has RAM. The Cyclone II family has internal RAM, but the EP2C8T1448 that we use in EEL 4712: Digital Design has only about 2kB. The Cyclone II family, EP2C70F896I8 device (the last on the list in Quartus) has 1,152,000 bit of RAM (= 144,000 bytes), which is more than 128kB. For our example we will use the Cyclone II family, EP2C70F896I8 device, so that we can use this part for both this example and in the future. 3. In your schematic (BDF f ile), add an “lpm_rom” component found in the “megafunctions” library under “storage.” Select “Launch MegaWizard Plug - In.” The MegaWizard Manager should now help you with the rest of your design. 4. It does not really matter what “type of output file” you cre ate, but I usually choose VHDL. The MagaWizard will give a default name. I suggest you use it. Select “Next.” 5. We will make a 1k x 8 bit device (1kB), so we’ll need 8 data bits and 10 address bits (210=1024 words). Answ er “8” for “How wide should the ‘q’ output bus be?” Answer “1024” for “How many 8
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