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Unformatted text preview: pipelined design. Explain why. (3) What is instruction level parallelism (ILP)? Give a HC12 code sequence that you wrote for your Lab, homework etc to prove the existence of ILP. (4) Explain the basic idea of cache and branch predictor. Why they can reduce program execution time? (5) Which hardware features need to be added if you are going to design a new version of HC12 that supports out-of-order and speculative execution? (6) Explain why exploiting ILP makes processing interrupts much more difficult?...
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This note was uploaded on 11/13/2011 for the course EEL 4744c taught by Professor Staff during the Fall '09 term at University of Florida.
- Fall '09