lecture5-6pg - Reading Assignment EEL 4744C: Microprocessor...

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1 Dr. Tao Li 1 EEL 4744C: Microprocessor Applications Lecture 5 68HC12 Instruction Set Dr. Tao Li 2 Software and Hardware Engineering (Old version) Chapter 4 Or Software and Hardware Engineering (New version) Chapter 7 And CPU12 Reference Manual Chapter 5 Reading Assignment Dr. Tao Li 3 68HC12 has >1000 instructions! They are grouped into a few (17) functional categories Besides operation , variance w.r.t. effect on CCR , available addressing modes , etc Details found in book as well as Motorola CPU Ref. Gui de (short) and CPU Ref. Manual (long) Some Tips Dr. Tao Li 4 Load registers Store registers Transfer/Exchange Registers Move memory contents Decrement/Increment Clear/Set Arithmetic Logic M68HC12 Instruction Set Categories Rotates/Shifts Data test Specialized math Conditional branch Loop primitive Jump and branch Condition code Interrupt Miscellaneous Dr. Tao Li 5 Load and Store Instructions 8-bit load and store instructions (LDAA, LDAB, STAA, STAB) 16-bit load and store instructions (LDD, LDS, LDX, LDY, STD, STS, STX, STY) MSB lower address (EA) LSB higher address (the next location) Dr. Tao Li 6 Endianness (Byte Order) Big endian : the most significant byte of multibyte data is stored at the lowest memory address Sun's SPARC, Motorola's 68K, and the PowerPC families Little endian : the least significant byte of multibyte data is stored at the lowest memory address Intel's 80x86 A little-endian memory dump
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2 Dr. Tao Li 7 Load Register Instructions Load Registers (see Section 4.4) Mnemonic LDAA LDD LDX LEAS LEAY Operation (M) 6 A (M:M+1) 6 D (M:M+1) 6 X EA 6 SP EA 6 Y Mnemonic LDAB LDS LDY LEAX Operation (M) 6 B (M:M+1) 6 SP (M:M+1) 6 Y EA 6 X PULA PULD PULX (SP) 6 A (SP:SP+1) 6 D (SP:SP+1) 6 X PULB PULC PULY (SP) 6 B (SP) 6 CCR (SP:SP+1) 6 Y Load memory data to Reg. Load stack element to Reg. Load effective address to Reg. See Freescale manual for supported addressing mode and impact on CCR Dr. Tao Li 8 Store Register Instructions Store Reg. data to memory Store Reg. data to stack Save CCR to stack See Freescale manual for supported addressing mode and impact on CCR Store Registers (see Section 4.4) Mnemonic STAA STD STX Operation A 6 (M) D 6 (M:M+1) X 6 (M:M+1) Mnemonic STAB STS STY Operation B 6 (M) SP 6 (M:M+1) Y 6 (M:M+1) PSHA PSHD PSHY A 6 (SP) D 6 (SP:SP+1) Y 6 (SP:SP+1) PSHB PSHC PSHX B 6 (SP) CCR 6 (SP) X 6 (SP:SP+1) Dr. Tao Li 9 What is Wrong with this Program? COUNT: EQU !8 ;Loop counter - - - ldab #COUNT ;Initialize loop counter - - - LOOP: - - - decb ; Decrement the B register and ; branch to LOOP if B register is ; not zero ldaa #$64 ; Load the A register with some ; data bne LOOP decb sets Z bit in CCR bne detects Z bit in CCR ldaa (accidentally) alters CCR Dr. Tao Li 10 Use LDS to initialize; access via PSHA, PSHB, PSHX, etc., PULA, PULB, PULX, etc.) Access is normally balanced (i.e. matching pushes
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lecture5-6pg - Reading Assignment EEL 4744C: Microprocessor...

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