lecture6-part1-4pg - Reading Assignment EEL 4744C:...

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1 Dr. Tao Li 1 EEL 4744C: Microprocessor Applications Lecture 6 Part 1 Dr. Tao Li 2 Software and Hardware Engineering (new version): page 17-20 OR Microcontrollers and Microcomputers: Chapter 7 Reading Assignment Dr. Tao Li 3 We need to transfer information, in parallel or in serial, in or out of the CPU, i.e. I/O I/O requires a hardware interface between the I/O devices and the computer bus Design the hardware interface to transfer code and data from multiple sources to the CPU, and from the CPU to multiple destinations, using a computer’s buses Design Statement Dr. Tao Li 4 A bus is a parallel, bidirectional, and binary information pathway with multiple sources and multiple destinations CPU is interconnected to memory and I/O devices through 3 kinds of buses: data, address, control Component-level bus: defined by the signals on the microprocessor chip, e.g. READ/WRITE System-level bus: defined by the signals on the backplane (system board), e.g. MEMRD, IORD Computer Bus
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2 Dr. Tao Li 5 A parallel 8-bit input interface can be constructed with 8 tri-state buffers whose enable (1G) lines are connected together, e.g. 74LS244 octal line driver Signal 1G must be asserted (= 0) to activate output The Input Interface Source Bus Dr. Tao Li 6 A latch is the interface between the data bus and the output device. Control signals for this latch are generated from the sequence controller, e.g. clock The Output Interface Dr. Tao Li 7 The interface must let CPU select from one of many sources and destinations of I/O. We can use decoders for selecting these READ_CONTROL is used to select the input source to read from WRITE_CONTROL is used to select the output destination to write to A0, A1, READ_CONTROL and WRITE_CONTROL are generated by the CPU (sequence controller) Dr. Tao Li 8 Address Decoding for Sources and Destinations Read Control
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Dr. Tao Li 9 The CPU must provide timing and synchronization so that the transfer of information occurs at the right time This means that data can only be taken from or placed onto the bus at the correct time Write cycle: transfer of data from a register to an output data latch Read cycle: transfer of data from an external source to the CPU (a register) Dr. Tao Li 10 CPU places the address on the address bus at point A. CPU timing is controlled by the clock Data bits are placed by CPU onto the data bus at point B The WRITE signal is asserted by CPU shortly after at point C The WRITE signal stays asserted long enough until point D, to let the data bits be latched Write Cycle Dr. Tao Li 11 Write Cycle Dr. Tao Li 12 CPU places the address on the address bus at point A. CPU timing is controlled by the clock The READ signal is asserted at point B to let the input device know that CPU is ready for data CPU begins taking data bits from the data bus
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lecture6-part1-4pg - Reading Assignment EEL 4744C:...

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