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Unformatted text preview: 1 Dr. Tao Li 1 EEL 4744C: Microprocessor Applications Lecture 7 Part 2 M68HC12 Interrupt Dr. Tao Li 2 • Software and Hardware Engineering (New version): Chapter 12 or • SHE (old version) Chapter 8 And • CPU12 Reference Manual Chapter 7 And • HC12 Data Sheet Chapter 4 Reading Assignment Dr. Tao Li 3 • What is an Interrupt? – an asynchronous event that stops normal program execution – performs a Service Route (i.e., executes some code) – returns program to where it left off • Why have IRQ's? 1) Good for Asynchronous Events- that must be serviced- don't want to use main CPU cycles to continually check 2) Good for Synchronizing with external processes- if CPU is faster than peripherals (printer, A/D, etc…)- peripherals notify CPU when they're ready- CPU doesn’t waste time "waiting" 3) Good for timed events- "Real Time Systems" events happen periodically- Multi-tasking Interrupts (IRQ) Dr. Tao Li 4 • Priority- interrupts can occur at the same time- some interrupts are more important than others (ex, fire alarm)- to handle this, all interrupts are given a default priority- some priorities can be changed • Interrupt Service Route (ISR)- this is the code to be executed when an IRQ occurs- each individual IRQ has an ISR if it is being used- this is similar to a subroutine, it is code written by us • Interrupt Vector Address- each IRQ has a unique Vector Address- this holds the address of ISR to be executed if that IRQ occurs Interrupt 101 2 Dr. Tao Li 5 • Uses vectored interrupts, but polling used when multiple external sources on IRQ* line • Features h/w priority resolution that can be customized via s/w • IRQ* and XIRQ* (NMI), plus other signals w/ timer subsystem, serial interface, and A/D converter that we’ll see in later chapters • Special interrupts including s/w, illegal opcode, watchdog timer, and clock failure interrupts HC12B32 Interrupt Overview External Internal Dr. Tao Li 6 • Interrupt vector is address of start of particular ISR • When interrupt generated, CPU fetches this address from vector location • Interrupt vector table for HC12B32 ¹ Interrupt Vectors IRQ* Pin XIRQ* Pin RESET* Dr. Tao Li 7 • IRQ detected • CPU finished current instruction • CPU pushes all registers onto the STACK – this includes the Program Counter, which is where the program will return to after the ISR • CPU grabs the ISR address from the "Vector Table" and loads into the PC • ISR is executed and completes • CPU pulls all registers from the STACK – this includes the Program Counter • CPU returns to executing code as it was before What Happens When an IRQ Happens Dr. Tao Li 8 • Request: IRQ occurs and indicates to CPU that it needs attention • Pending: IRQ that is waiting to be serviced • Service: Process of executing the ISR • Latency: The delay between the Request and the beginning of Service Finish executing current instruction Storing CPU registers to STACK Retrieve ISR address from Vector Table +__________________________________ Latency Terminology 3...
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This note was uploaded on 11/13/2011 for the course EEL 4744c taught by Professor Staff during the Fall '09 term at University of Florida.
- Fall '09