lecture9-part2 - EEL 4744C: Microprocessor Applications...

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Dr. Tao Li 1 EEL 4744C: Microprocessor Applications Lecture 9 Part 2 M68HC12 Serial I/O
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Dr. Tao Li 2 Software and Hardware Engineering (new version): Chapter 15 SHE (old version): Chapter 11 HC12 Data Sheet: Chapter 14 Reading Assignment
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Dr. Tao Li 3 Asynchronous serial communication interface (SCI), a.k.a. on-chip UART; 1 on B32, 2 on A4 Synchronous serial peripheral interface (SPI) for high- speed synchronous serial communication Also a byte data link communication (BDLC) module on B32 for SAE J1850 communication in auto. applications (will not be discussed) Introduction
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Dr. Tao Li 4 Basic SCI & SPI Layout
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Dr. Tao Li 5 Full-duplex, h/w parity generation, option for single-wire operation On-chip generator for standard bit-rates Transmitter and receiver double-buffered, operate independently, use same rate and format Supports 8- or 9-bit data, variety of flags and interrupts Asynchronous Serial Communication Interface
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Dr. Tao Li 6 Programming and using SCI includes three components: Initialization of data rate, word length, parity, and interrupting capabilities Writing to SCI data register (being careful not to exceed transmission rate) Reading from SCI data register (being careful to read incoming data before more arrives) Asynchronous Serial Communication Interface
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Dr. Tao Li 7 Two data regs., SCnDRH and SCnDRL (n=0 on B32 and =0,1 on A4) SCnDRL reg. is two separate regs. at same address, one for read and one for write SCnDRH for MSB of 9-bit data, should be written before SCnDRL for correct data transfer If 8-bit data, only SCnDRL used SCI Data
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Dr. Tao Li 8 SCI Data Register
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Dr. Tao Li 9 Control bits TE and RE in SCnCR2 to enable transmitter and receiver on each SCI channel SCI operation mode must be initialized using SCnCR1 In addition to normal SCI operation (default), several other modes available: Wired-OR mode (output pin is open-drain; needs external pullup; used in single-wire system with multiple devices connected together); controlled by WOMS control bit SCI I nitialization
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Dr. Tao Li 10 Loop mode (for testing, if rec. source bit RSRC = 0 then rec. connected internally to xmitter and thus xmitter can be disconnected from TxD pin; o/w external) SCI I nitialization
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Dr. Tao Li 11 Single-wire mode (only TxD pin(s) used, and RxD pins available for GP I/O) SCI I nitialization
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Dr. Tao Li 12 M control bit: (‘0’ means 1 start, 8 data, and 1 stop bit; ‘1’ means 1, 9, and 1) H/w to detect idle line (receive line in mark (1) state for more than one character time) H/w to generate parity bit; enabled via PE bit, type
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lecture9-part2 - EEL 4744C: Microprocessor Applications...

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