csee4824_f11_lec03

csee4824_f11_lec03 - 5 CSEE 4824 Fall 2011 - Lecture 3 Page...

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Unformatted text preview: 5 CSEE 4824 Fall 2011 - Lecture 3 Page 10 Luca Carloni Columbia University ISA: Articulation Point between HW & SW Articulation point of the design process decouples implementation and specification the HW implementation of the microprocessor is decoupled from the specification of the instruction set decouples high-level and programs languages from the abstract machine through the role played by the compiler/interpreter the 80x86 ISA Intel 80x86 MP3 player written in C Pentium 4 MP3 player written in Java CSEE 4824 Fall 2011 - Lecture 3 Page 11 Luca Carloni Columbia University Taxonomy of ISAs The type of internal storage, the most basic differentiation, distinguishes the ISAs Accumulator Architectures Stack Architectures General Purpose Register (GPR) Architectures Register-Memory Architectures Register-Register (load-store) Architectures Memory-Memory Architectures GPRs faster access to temporaries, smarter compilation, less memory traffic ALU memory reg reg reg processor stack 6 CSEE 4824 Fall 2011 - Lecture 3 Page 12 Luca Carloni Columbia University Taxonomy of ISAs: Accumulator a = b + (c * d) memory ALU processor load c mul d add b store a Instruction operands 1 explicit, 1 implicit acc m acc + *mem acc m *mem *mem m acc Pros short instruction simple design Cons inefficient code many transfers pipelining is hard Examples Early machines (EDSAC, IAS) acc CSEE 4824 Fall 2011 - Lecture 3 Page 13 Luca Carloni Columbia University Taxonomy of ISAs: Stack a = b + (c * d) memory ALU processor stack push b push c push d mul add pop a Instruction operands none (implicit) for ALU operations one for transfer from/to memory push/pop Pros short instruction simple compiler Cons inefficient code many swaps, copies stack may be slow Examples B5000, JVM 7 CSEE 4824 Fall 2011 - Lecture 3 Page 14 Luca Carloni Columbia University Taxonomy of ISAs: Register-Memory a = b + (c * d) load r1, c mul r1, r1, d add r1, r1, b store r1, a Instruction operands 2 (typically) one from memory Pros fewer instructions dense encoding Cons operand asymmetry result destroys one instr. asymmetry different CPIs Examples IBM 360, 80x86, Motorola 68000, TI TMS320C54x memory ALU processor reg reg reg CSEE 4824 Fall 2011 - Lecture 3 Page 15 Luca Carloni Columbia University Taxonomy of ISAs: Memory-Memory a = b + (c * d) mul e, c, d add a, e, b Instruction operands 2 or 3 operands all from memory Pros most compact instruction count no need of registers Cons large variation in instruction lengths very different CPIs high memory traffic Examples VAX (some instr.) not used nowadays memory ALU processor 7 CSEE 4824 Fall 2011 - Lecture 3 Page 14 Luca Carloni Columbia University...
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This note was uploaded on 11/12/2011 for the course CSEE 4824 taught by Professor Carloni during the Fall '11 term at Columbia.

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csee4824_f11_lec03 - 5 CSEE 4824 Fall 2011 - Lecture 3 Page...

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