csee4824_f11_lec04

csee4824_f11_lec04 - 3 CSEE 4824 – Fall 2011 - Lecture 4...

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Unformatted text preview: 3 CSEE 4824 – Fall 2011 - Lecture 4 Page 5 Luca Carloni – Columbia University /* Assumptions: a,b: arrays of 64- bit integers c,i: 64-bit integers all values and addresses are in memory at 0 : A 5000 : B 1500 : C 2000 : i */ for (i=0; i<100; i++) { a[i] = a[i] + b[i] - c; } Example: Compiling a Simple Code Fragment for MIPS64 (Unoptimized Version) executed instructions = 2 + (11 * 100) = 1102 exec. mem. data references = 1 + (6*100)=601 code size (in bytes) = 4 * 13 = 52 Note: for now assume that values in the registers are lost between consecutive iterations of the loop R1, 2000(R0) R6, 0(R1) R1, 2000(R0) CSEE 4824 – Fall 2011 - Lecture 4 Page 6 Luca Carloni – Columbia University Example: Compiling a Simple Code Fragment for MIPS64 (Optimized Version) /* Assumptions: a,b: arrays of 64- bit integers c,i: 64-bit integers all values and addresses are in memory at 0 : A 5000 : B 1500 : C 2000 : i */ for (i=0; i<100; i++) { a[i] = a[i] + b[i] - c; } 73% 50% 77% executed instructions = 2 + (8 * 100) = 802 exec. mem. data references = 1 + (3*100)=301 code size (in bytes) = 4 * 10 = 40 executed instructions = 2 + (11 * 100) = 1102 exec. mem. data references = 1 + (6*100)=601 code size (in bytes) = 4 * 13 = 52 R2, 0(R1) 4 CSEE 4824 – Fall 2011 - Lecture 4 Page 7 Luca Carloni – Columbia University Example: Compiling a Simple Code Fragment for MIPS64 (One More Optimization) /* Assumptions: a,b: arrays of 64- bit integers c,i: 64-bit integers all values and addresses are in memory at 0 : A 5000 : B 1500 : C 2000 : i */ for (i=0; i<100; i++) { a[i] = a[i] + b[i] - c; } 88%-- executed instructions = 2 + (8 * 100) = 802 exec. mem. data references = 1 + (3*100)=301 code size (in bytes) = 4 * 10 = 40 executed instructions = 3 + (7 * 100) = 703 exec. mem. data references = 1 + (3*100)=301 code size (in bytes) = 4 * 10 = 40 R2, 0(R1) CSEE 4824 – Fall 2011 - Lecture 4 Page 8 Luca Carloni – Columbia University Simple Implementation of a MIPS Subset (1) : Multi-Cycle and Non-Pipelined Design 1. IR m Mem[PC]; NPC m PC+4; 2. A m Regs[rs]; B m Regs[rt]; Imm m signExt( IR 16 ) • fixed-f ield decoding 3. one of the followings:- ALUOutput m A + Imm- ALUOutput m func (A, B)- ALUOutput m A op Imm- Cond m (A == zero) and ALUOutput m NPC + (Imm <<2) 4. PC m MUX(cond, ALUOutput, NPC)- LMD m Mem[ALUOutput] or- Mem[ALUOutput] m B 5. one of the followings:- Regs[rd] m ALUOutput- Regs[rt] m ALUOutput- Regs[rt] m LMD • temporary registers •hold values between clock cycles for an instruction • state elements (“visible part of the state”) •hold values between successive instructions • control logic (FSM or microcode controller) • (not illustrated in the diagram above) 5 CSEE 4824 – Fall 2011 - Lecture 4 Page 9 Luca Carloni – Columbia University Simple Implementation of a MIPS Subset (1) : Multi-Cycle and Non-Pipelined Design • temporary registers •hold values between clock cycles for an instruction • state elements (“visible part of the state”)...
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This note was uploaded on 11/12/2011 for the course CSEE 4824 taught by Professor Carloni during the Fall '11 term at Columbia.

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csee4824_f11_lec04 - 3 CSEE 4824 – Fall 2011 - Lecture 4...

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