csee4824_f11_lec06

csee4824_f11_lec06 - Pipeline Hazards and Their...

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4 CSEE 4824 – Fall 2011 - Lecture 6 Page 7 Luca Carloni – Columbia University Pipeline Hazards and Their Classification •P i p e l i n e h a z a r d s i t u a t i o n “the next instruction cannot execute in the following clock cycle” •P i p e l i n e h a z a r d s c om
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5 CSEE 4824 – Fall 2011 - Lecture 6 Page 9 Luca Carloni – Columbia University Pipeline Stalls (or Bubbles): Example of Loading/ Fetching from a Unified Single-Port Memory A bubble always increases the CPI of the microprocessor implementation •S t r u c t u r a l hazard causes a bubble –i t f l o a t s through the pipeline taking space but carrying no useful information WB MEM EX ID IF ADD R12, R3, R4 WB MEM EX ID IF ADD R14, R5, R6 STALL WB MEM EX ID IF SUB R11, R2, R3 WB MEM EX ID IF LW R10, 20(R1) 9 8 7 6 5 4 3 2 1 instruction CSEE 4824 – Fall 2011 - Lecture 6 Page 10 Luca Carloni – Columbia University Impact of Stalls on the Performance of Pipelined Implementation •S p e c i a l c
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6 CSEE 4824 – Fall 2011 - Lecture 6 Page 11 Luca Carloni – Columbia University
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This note was uploaded on 11/12/2011 for the course CSEE 4824 taught by Professor Carloni during the Fall '11 term at Columbia.

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csee4824_f11_lec06 - Pipeline Hazards and Their...

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