csee4824_f11_lec07

csee4824_f11_lec07 - Review Dealing with Data Hazards...

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2 CSEE 4824 – Fall 2010 - Lecture 7 Page 3 Luca Carloni – Columbia University Review: Dealing with Data Hazards through Forwarding and Pipeline Interlocks •… w h e n forwarding is not possible… –b e c a u s e w e can’t operate backward in time! •…w e n e e d a different HW solution –p i p e l i n e interlocks introduce stalls in the middle of an instruction Interlocks are implemented using NOPs ; a NOP is an instruction that does nothing. For instance DADD R0, R0, R0 CSEE 4824 – Fall 2010 - Lecture 7 Page 4 Luca Carloni – Columbia University Pipeline Stalls due to Interlocks WB MEM EX ID ID IF AND R6, R1, R7 WB MEM EX ID IF OR R8, R1, R9 STALL WB MEM EX EX ID IF DSUB R4, R1, R5 WB MEM EX ID IF LD R1, 0(R2) 9 8 7 6 5 4 3 2 1 instruction A NOP Instruction (a bubble) that is
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3 CSEE 4824 – Fall 2010 - Lecture 7 Page 5 Luca Carloni – Columbia University Reducing Pipeline Branch Penalties - III: Branch Delaying •T h e i n s t r u c t i o n i n the delay slot is executed whether or not the branch is taken Three strategies to fill the delay slot a) always best choice if possible b) preferred when branch is taken with high probability –e . g . , l o o p b r a n c h e s c) dual case as (b) Strategies (b) and (c) can be applied only if it is ok to execute the moved instruction if the prediction is wrong (i.e. the processor state is not affected) CSEE 4824 – Fall 2010 - Lecture 7 Page 6 Luca Carloni – Columbia University Example: Branch Penalty (in CPI units) on the MIPS R4000 Processor 3 0 2 Predict Untaken 2 3 2 Predict Taken 3 3 2 Flush Pipeline Penalty taken Penalty untaken Penalty (uncond. branch) Branch scheme 0.30 0.20 0.30
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4 CSEE 4824 – Fall 2010 - Lecture 7 Page 7 Luca Carloni – Columbia University MIPS Pipeline: Control Implementation with Forwarding and Interlocking •s CSEE 4824 – Fall 2010 - Lecture 7 Page 8 Luca Carloni – Columbia University MIPS Pipeline: Control Implementation with Forwarding and Interlocking – cont. if ( ID/EX .MemRead and ( ( ID/EX .[rt] == IF/ID .[rs] ) or ( ID/EX .[rt] == IF/ID .[rt] ) stall the pipeline if ( EX/MEM .RegWrite ( EX/MEM .[rd] z R0) ( EX/MEM .[rd] = ID/EX .[rs])) forward ALUOutput to A •S i m i l a r c e c k s o register rt for possible forwarding to other ALU input (B) if ( MEM/WB .RegWrite and (
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This note was uploaded on 11/12/2011 for the course CSEE 4824 taught by Professor Carloni during the Fall '11 term at Columbia.

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csee4824_f11_lec07 - Review Dealing with Data Hazards...

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