csee4824_f11_lec09

csee4824_f11_lec09 - CSEE W4824 Computer Architecture Fall...

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1 CSEE W4824 – Computer Architecture Fall 2011 Luca Carloni Department of Computer Science Columbia University in the City of New York http://www.cs.columbia.edu/~cs4824/ Lecture 9 Memory Hierarchy Design: The Basics of Caches CSEE 4824 – Fall 2011 - Lecture 9 Page 3 Luca Carloni – Columbia University The Processor-Memory Performance Gap •C P U s p e e d
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2 CSEE 4824 – Fall 2011 - Lecture 9 Page 4 Luca Carloni – Columbia University Typical PC Organization Source: B. Jacob et al. “Memory Systems” CSEE 4824 – Fall 2011 - Lecture 9 Page 5 Luca Carloni – Columbia University DSP-Style Memory System: Example based on TI TMS320C3x DSP family • dual tag-less on-chip SRAMs (visible to programmer) • off-chip programmable ROM (or PROM or FLASH) that holds the executable image •o
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3 CSEE 4824 – Fall 2011 - Lecture 9 Page 6 Luca Carloni – Columbia University Memory Technology • At the core of the success of computers • Various types of memory – most common types • DRAM (Dynamic Random Access Memory) • SRAM (Static Random Access Memory) • ROM (Read Only Memory) •F la sh Memo ry • Memory Latency Metrics – Access time • time between when a “read” is requested and when the desired word arrives – Cycle time ( Access time) • minimum time between two requests to memory • memory needs the address lines to be stable between accesses CSEE 4824 – Fall 2011 - Lecture 9 Page 7 Luca Carloni – Columbia University Logical Organization of a 64M-Bit DRAM • Highest memory cell density – only 1 transistor used to store 1 bit – to prevent data loss, each bit must be refreshed periodically • DRAM access periodically all bits in every row (refresh)
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4 CSEE 4824 – Fall 2011 - Lecture 9 Page 8 Luca Carloni – Columbia University Logical Organization of Wide Data-Out DRAMs • In order to output more than one bit at a time, the DRAM is organized internally with multiple arrays , each providing one bit towards the aggregate output • Wider output DRAMs have appeared in the last two decades – parts with x16 and x32 data widths are now common, used primarily in high-performance applications Source: B. Jacob et al. “Memory Systems” CSEE 4824 – Fall 2011 - Lecture 9 Page 9 Luca Carloni – Columbia University DIMMs, Ranks, Banks, and Arrays • A memory system may have many DIMM s, each of which may contain one or more
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csee4824_f11_lec09 - CSEE W4824 Computer Architecture Fall...

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