1CSEE W4824 – Computer ArchitectureFall 2011Luca CarloniDepartment of Computer ScienceColumbia University in the City of New Yorkhttp://www.cs.columbia.edu/~cs4824/Lecture 9Memory Hierarchy Design:The Basics of CachesCSEE 4824 – Fall 2011 - Lecture 9Page 3Luca Carloni – Columbia UniversityThe Processor-Memory Performance Gap •CPU speed –assumes 25% improvement per year until 1986, 52% improvement until 2004 and 25% improvement thereafter•Memory Baseline: –64KB DRAM w/ 150-250ns latency in 1980, 7% per year latency improvement•Architects must attempt to work around this gap to minimize the memory bottleneck (log scale)
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2CSEE 4824 – Fall 2011 - Lecture 9Page 4Luca Carloni – Columbia UniversityTypical PC OrganizationSource: B. Jacob et al. “Memory Systems”CSEE 4824 – Fall 2011 - Lecture 9Page 5Luca Carloni – Columbia UniversityDSP-Style Memory System: Example based on TI TMS320C3x DSP family•dual tag-less on-chip SRAMs (visible to programmer)•off-chip programmable ROM (or PROM or FLASH) that holds the executable image •off-chip DRAM used for computationSource: B. Jacob et al. “Memory Systems”