csee4824_f11_lec12

csee4824_f11_lec12 - 4 CSEE 4824 Fall 2011 - Lecture 12...

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Unformatted text preview: 4 CSEE 4824 Fall 2011 - Lecture 12 Page 7 Luca Carloni Columbia University Review: Dynamic Scheduling with Scoreboard Goal when possible, execute instructions following a stall Strategy in-order issuing out-of-order execution out-of-order completion Implementation centralized control read operands together when they are all avaialable Hazard handling Structural and WAW stall issuing RAW solved dynamically WAR stall committing CSEE 4824 Fall 2011 - Lecture 12 Page 8 Luca Carloni Columbia University Multiple-Issue Processors Superscalars issue a varying number of instructions per clock cycle either statically scheduled by the compiler using in-order execution or dynamically scheduled by the hardware using out-of-order execution (techniques like Tomasulo Algorithm) VLIW (Very Long Instruction Words) Processors issue a fixed number of instructions formatted either as one large instruction, or a fixed instruction packet with parallelism explicitly indicated by the instruction (EPIC for IA-64 in Itanium processors) inherently statically scheduled by the compiler 5 CSEE 4824 Fall 2011 - Lecture 12 Page 9 Luca Carloni Columbia University Example: Ideal Pipeline Execution for Static Dual-Issue MIPS Datapath WB MEM EX ID IF load/ store WB MEM EX ID IF ALU/branch WB MEM EX ID IF load/ store WB MEM EX ID IF ALU/branch WB MEM EX ID IF load/ store WB MEM EX ID IF ALU/branch WB MEM EX ID IF load/ store WB MEM EX ID IF ALU/branch Inst. Type CSEE 4824 Fall 2011 - Lecture 12 Page 10 Luca Carloni Columbia University Example: Static Dual-Issue MIPS Datapath Additional resources second port from instruction memory additional ports to/from reg. file additional ALU for memory address calculation 6 CSEE 4824 Fall 2011 - Lecture 12 Page 11 Luca Carloni Columbia University Tomasulos Algorithm (1967) Invented by Robert M. Tomasulo for IBM 360/91 (about three years after CDC 6600) CSEE 4824 Fall 2011 - Lecture 12 Page 12 Luca Carloni Columbia University Dynamic Scheduling with Tomasulos Algorithm Motivations need for improving performance of floating-point unit for the whole IBM 360 family (without specialized compilers) IBM 360 had only 4 DP FP registers (limiting the effectiveness of compiler scheduling) IBM 360 had long memory access and long FP delays Main features distributed control and buffering with reservation stations dynamically replace register specification in instruction with value or pointer to functional unit producing the value ( register renaming ) handle efficiently WARs and WAWs tracking when operands are available to handle RAWs more reservation stations than registers eliminates name dependencies that compiler cant eliminate Basic concepts reused in many other architectures Alpha 21264, Pentium II, III, IV, PowerPC, MIPS R10000, AMD K5 7...
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This note was uploaded on 11/12/2011 for the course CSEE 4824 taught by Professor Carloni during the Fall '11 term at Columbia.

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csee4824_f11_lec12 - 4 CSEE 4824 Fall 2011 - Lecture 12...

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