csee4824_f11_lec05

csee4824_f11_lec05 - 1 CSEE W4824 – Computer Architecture...

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Unformatted text preview: 1 CSEE W4824 – Computer Architecture Fall 2011 Prof. Luca Carloni Department of Computer Science Columbia University in the City of New York http://www1.cs.columbia.edu/~cs4824/ Lecture 5 IC Fabrication Costs and the Role of EDA Page 2 CSEE 4824 – Fall 2011 - Lecture 5 Luca Carloni – Columbia University Quick Review of Some Prerequisite Material – 1 Combinational vs. Sequential Logic combinational logic (no state) memory elements (carrying state) 2 Page 3 CSEE 4824 – Fall 2011 - Lecture 5 Luca Carloni – Columbia University Example: The Truth Table of the Three-Bit Decoder Page 4 CSEE 4824 – Fall 2011 - Lecture 5 Luca Carloni – Columbia University Example: Truth Table and Logic Equations for a Full Adder 3 Page 5 CSEE 4824 – Fall 2011 - Lecture 5 Luca Carloni – Columbia University Example: Composing Logical Blocks to Build a Register File Page 6 CSEE 4824 – Fall 2011 - Lecture 5 Luca Carloni – Columbia University Quick Review of Some Prerequisite Material – 3 (Synchronous) Finite State Machines Mealy FSM 4 Page 7 CSEE 4824 – Fall 2011 - Lecture 5 Luca Carloni – Columbia University FSM Example: Traffic Light Controller - Specification Page 8 CSEE 4824 – Fall 2011 - Lecture 5 Luca Carloni – Columbia University FSM Example: Traffic Light Controller – Implementation (State Assignment, Minimization,…) 5 Page 10 CSEE 4824 – Fall 2011 - Lecture 5 Luca Carloni – Columbia University Quick Review of Some Prerequisite Material – 3 Timing Issues - Constraints on the Clock Period CCT ≥ t_prop + t_combinational + t_setup + • Races are avoided and functional correctness is guaranteed as long as the clock period satisfies the following constraint t_skew Page 11 CSEE 4824 – Fall 2011 - Lecture 5 Luca Carloni – Columbia University Quick Review of Some Prerequisite Material – 4 Synchronous Design and Sequential Modules output registers state registers primary outputs primary inputs combinational logic • any path between a primary input and a primary output contains at least one register • state and output registers are controlled by a common clock signal 6 Page 12 CSEE 4824 – Fall 2011 - Lecture 5 Luca Carloni – Columbia University Quick Review of Some Prerequisite Material – 5 Synchronous Register-Transfer Level (RTL) Design...
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This note was uploaded on 11/12/2011 for the course CSEE 4824 taught by Professor Carloni during the Fall '11 term at Columbia.

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csee4824_f11_lec05 - 1 CSEE W4824 – Computer Architecture...

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