csee4824_f11_lec14

csee4824_f11_lec14 - CSEE W4824 Computer Architecture Fall...

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1 CSEE W4824 – Computer Architecture Fall 2011 Luca Carloni Department of Computer Science Columbia University in the City of New York http://www.cs.columbia.edu/~cs4824/ Lecture 14 Hardware-Based Speculative Execution CSEE 4824 – Fall 2011 - Lecture 14 Page 2 Luca Carloni – Columbia University Announcements •M id t e rm : Monday, October 31 In class, 75 minutes – OPEN BOOK and OPEN NOTES – NO ELECTRONIC EQUIPMENT MAY BE USED – Material covered by the midterm FROM LECTURE #1 UNTIL LECTURE #12 INCLUDED • Special Session: Midterm Review – Friday 10/28 from 12:30pm to 2:15pm in 833 Mudd – TAs will lead the session by discussing the solution of the practice midterm and answering general questions • Reminder: HW #3 is due this Wed 10/26 – solutions will be distributed shortly after class
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2 CSEE 4824 – Fall 2011 - Lecture 14 Page 3 Luca Carloni – Columbia University Announcements: CS Distinguished Lecture Wed, Oct. 26 th 11:00 am - Davis Auditorium CSEE 4824 – Fall 2011 - Lecture 14 Page 4 Luca Carloni – Columbia University Review: Dynamic Branch Prediction • Prediction decision change dynamically based on the behavior of the branch at run time • Techniques – 2-bit Predictors • better than 1-bit predictors in handling loops (hysteresis) – (2,2)-bit Correlation Predictors • often outperform 2-bit predictors by better handling nested branches – Branch-Target Buffer • allows to predict the branch-target address earlier with respect to schemes based on a branch-history table • branch penalties due –t ab l e m i s s – mispredictions
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3 CSEE 4824 – Fall 2011 - Lecture 14 Page 5 Luca Carloni – Columbia University The Concept of Speculation • The compiler (or the processor) guesses the outcome of an instruction to remove it as a dependency in executing other instructions – speculate the outcome of a branch to anticipate the execution of the instructions after the branch – speculate that a load following a store does not refer to the same address to anticipate the load execution • Implementation Overhead –mechan i sm to check if the guess was right i unroll the effects of wrong speculations •in SW , the compiler adds additional instruction that check the correctness of speculation and possibly invoke a “fix-up routine” HW , the result of speculated instructions are buffered until they can be committed in order after speculation is resolved CSEE 4824 – Fall 2011 - Lecture 14 Page 6 Luca Carloni – Columbia University Hardware-Based Speculation • Combination of three concepts – out-of-order execution via dynamic scheduling – dynamic branch prediction – speculative execution of instructions • More parallelism – parallel execution of instruction across basic blocks • Implementation: Extending Tomasulo’s Algorithm • e.g.: PowerPC, MIPS R10000, Pentium II,III,IV, Alpha 21264 – key idea • separate instruction by-passing from committing • in-order issue ; out-of-order execute ; in-order commit – key hardware component • reorder buffer
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4 CSEE 4824 – Fall 2011 - Lecture 14 Page 7
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This note was uploaded on 11/12/2011 for the course CSEE 4824 taught by Professor Carloni during the Fall '11 term at Columbia.

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csee4824_f11_lec14 - CSEE W4824 Computer Architecture Fall...

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